RISC computer with unaligned reference handling and method for the same

Claim 2

In a reduced instruction set computer with a memory holding m-bit words separated by word boundaries, a device for retrieving an unaligned reference from said memory comprising: a. a general register; b. means for retrieving a first word containing a first portion of said unaligned reference in response to a nth instruction and a second word containing a second portion of said unaligned reference from said memory in response to an (n+k)th instruction; c. shifting means for shifting said first portion to a first position and second portion to a second position; and d. combining means for combining said first and second portions in said general register, wherein k and n are positive integers.

Claim 3

In reduced instruction set computer, a device for storing an unaligned reference into a memory with m-bit locations comprising: shifting means for shifting said unaligned reference in a first direction in response to an nth instruction and in a second direction in response to (n+k)th instruction, said means generating sequentially a first and second portion each having less than m-bits; and means for storing said first and second portions sequentially into said memory, wherein k and n are positive integers.

Claim 4

In reduced instruction set computer, a device for storing an unaligned reference into a memory with m-bit locations comprising: shifting means for shifting said unaligned reference in a first direction in response to an nth instruction and in a second direction in response to (n+k)th instruction, said means generating sequentially a first and second portion each having less than m-bits; and means for storing said first and second portions sequentially into said memory, wherein k and n are positive integers.

Claim 5

In a reduced instruction set computer with a memory for holding m-bit words, a device for loading a first unaligned reference having first and second portions of less than m-bits, said first portion being stored into a first section of said memory and said second portion being stored into a second section of said memory, and for storing a second aligned reference into said first and said second sections, comprising: a shift/merge unit having first and second inputs and being provided to shift first data bytes received from said first input, said first input being coupled to said memory unit to receive said first and second portions sequentially, and merge said first data bytes with second data bytes from said second input to form an m-bit word; a first latch means for storing said first and second data bytes, said latch having an output coupled to said second input; an m-bit general register coupled to said first latch means and provided for holding selectively one of said first or second unaligned references; a second latch means coupled to said register for storing said second unaligned reference; shifting means for shifting said second unaligned references; and output means for storing said second unaligned reference after shifting by said shifting means into said memory.

Claim 6

In a reduced instruction set computer with a memory for holding m-bit words, a device for loading a first unaligned reference having first and second portions of less than m-bits, said first portion being stored into a first section of said memory and said second portion being stored into a second section of said memory, and for storing a second aligned reference into said first and said second sections, comprising: a shift/merge unit having first and second inputs and being provided to shift first data bytes received from said first input, said first input being coupled to said memory unit to receive said first and second portions sequentially, and merge said first data bytes with second data bytes from said second input to form an m-bit word; a first latch means for storing said first and second data bytes, said latch having an output coupled to said second input; an m-bit general register coupled to said first latch means and provided for holding selectively one of said first or second unaligned references; a second latch means coupled to said register for storing said second unaligned reference; shifting means for shifting said second unaligned references; and output means for storing said second unaligned reference after shifting by said shifting means into said memory.

Claim 7

The device of claim 3 wherein said shift/merge unit shifts bytes received from said memory in a first direction in response to a first load instruction, and in a second direction in response to a second load instruction.

Claim 8

The device of claim 3 wherein said shifting means shifts bytes received from said second latch means in a first direction in response to a first store instruction, and in a second direction in response to a second store instruction.

Claim 9

The device of claim 3 further comprising a bypass multiplexer for selectively coupling to said second input one of the outputs of said first and second latching means.

Claim 10

The device of claim 4 wherein said first and second load instructions are at least partially overlapped.

Claim 11

The device of claim 5 wherein said first and second store instructions are at least partially overlapped.

Claim 14

The method of claim 9 wherein said first and second positions are defined by said nth and (n+k)th instruction respectively.

Claim 15

The method of claim 9 wherein said nth and (n+k)th instructions are overlapped.

Claim 18

The method of claim 12 wherein said first and second position are defined by said nth and (n+k)th instruction respectively.

Claim 19

The method of claim 12 wherein said nth and (n+k)th instructions are overlapped.