Patent JPS5632095A successfully refreshed from Google Patents.
Patent US3191126A successfully refreshed from Google Patents.
EP0442690A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Data cache store buffer for high performance computer
Assignee: HP Inc
•
Filing: 1991-02-12
•
Granted: —
•
Expires: 2011-02-12
Abstract
Abstract A data cache store buffer can be used to buffer stores between a CPU and its data cache to increase processor capability and reduce performance degradations caused by stores.
Inventors
- 👤 Thomas R. Hotchkiss
- 👤 Stephen R. Undy
- 👤 Daniel Lee Halperin
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-03 04:48
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0844; G06F12/0855
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
89 words
A data cache buffer for a computer comprising: a processing means for executing commands and performing operations on data, having an input for receiving information and an output for sending information; a buffer means having an input connected to the output of the processing means, the input for receiving information from the processing means, and for storing that information, and having an output; a data cache means having an input connected to the buffer means, the input for receiving information from the buffer means, and for storing that information.
Claim 2
Dependent Claim
40 words
The apparatus of claim 1 wherein the buffer means stores the information from the processor until the data cache means is accessible and the data cache means can receive and store the information without causing a stall in the processor.
Claim 3
Dependent Claim
30 words
The apparatus of claim 2 wherein the buffer means further comprises: a data store means for storing data; an address store means for storing the address location of the data.
Claim 4
Dependent Claim
53 words
The apparatus of claim 3 wherein the buffer store means further comprises a entry, the entry comprising: a validity indicator means for providing an indication whether the data located at the entry is valid; a data store means for storing data; an address store means for storing an address corresponding to the data.
Claim 5
Dependent Claim
34 words
The apparatus of claim 4 wherein the buffer store means is a two-way set associative and the entry further comprises a group indicator to indicate which data is being accesses by the processor means.
Claim 6
Dependent Claim
15 words
The apparatus of claim 5 wherein the store buffer means comprises a plurality of entries.
Claim 7
Dependent Claim
34 words
The apparatus of claim 2 wherein the data cache is a write-through data cache and the apparatus further comprises a main memory means for providing complete memory support to the data cache and processor.
Claim 8
Dependent Claim
34 words
The apparatus of claim 2 wherein the data cache is a write-back data cache and the apparatus further comprises a main memory means for providing complete memory support to the data cache and processor.
Claim 9
Dependent Claim
74 words
A data cache buffer for a computer comprising: a processor for executing loads and stores of information, the processor having an output; a buffer having an input connected to the output of the processor, the buffer receiving information from the processor, the buffer having an output, stores the information from the processor; a data cache having an input connected to the output of the buffer, the data cache receives the information from the buffer.
Claim 10
Independent Claim
68 words
A method for performing a store operation in an equivalent time it takes for performing a load operation, for a system having a processor, a data cache, a system bus, and a buffer, the method comprising the steps of: sending information from a processor to a buffer; writing the buffer information to a data cache; writing the data cache to a main memory at a subsequent predetermined time.
Claim 11
Dependent Claim
78 words
The method of claim 10, 11 further comprising the steps of: sending an address corresponding to information sought by the processor to the buffer; comparing the address sent to an address stored in the buffer; determining whether a match occurs; writing data into the buffer to be stored at the address in the buffer if a match occurs; determining whether buffer has an open entry; writing data at the open entry in the buffer if no match occurs.
Claim 12
Dependent Claim
68 words
The method of claim 10, 11 further comprising the steps of loading information into the buffer, the method comprising the steps of: comparing an address, sent by the processor in order to retrieve data corresponding to the address, to an address in the buffer; determining whether a match occurs; determining whether data is valid; sending data corresponding to the address if a match occurs and data is valid.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.