Store queue for a tightly coupled multiple processor configuration with two-level cache buffer storage

Claim 2

In a multiprocessor system having a plurality of processors including a first processor and at least one second processor, a first level cache connected to each processor, a single second level cache connected to each first level cache and shared by the processors, and a third level main memory connected to the second level cache, a system for queuing and buffering data and/or instructions, comprising: a first level store queue means associated with each processor and having an input connected to its corresponding processor and connected to an input of its corresponding first level cache for receiving said data and/or instructions from said its corresponding processor intended for potential storage in said its corresponding first level cache and for queuing said data and/or instructions therein simultaneously with in its corresponding first level cache, each of the first level store queue means having outputs; and a plurality of second level store queue means each of which is associated with a first level store queue means and interconnected between the output of such associated first level store queue means and an input of the single second level cache for receiving said data and/or instructions from said first level store queue means and for queuing said data and/or instructions therein prior to storage of said data and/or instruction in said second level cache, said first and second level store queues temporarily holding data and/or instructions to prevent the first processor from delaying its execution of additional instructions due to the second level cache being being busy with a store operation associated with a second processor.

Claim 3

In a multiprocessor system having a plurality of processors including a first processor and at least one second processor, a first level cache connected to each processor, a single second level cache connected to each first level cache and shared by the processors, and a third level main memory connected to the second level cache, a system for queuing and buffering data and/or instructions, comprising: a first level store queue means associated with each processor and having an input connected to its corresponding processor and connected to an input of its corresponding first level cache for receiving said data and/or instructions from said its corresponding processor intended for potential storage in said its corresponding first level cache and for queuing said data and/or instructions therein, each of the first level store queue means having outputs; a plurality of second level store queue means each of which is associated with a first level store queue means and interconnected between the output of such associated first level store queue means and an input of the single second level cache for receiving said data and/or instructions from said first level store queue means and for queuing said data and/or instructions therein prior to storage of said data and/or instruction in said second level cache; and wherein each said second level store queue means comprise a queue means connected to the output of its first level store queue means for receiving said data and/or instructions from said its respective first level store queue means and initially storing said data and/or instructions therein; and write buffer and control means connected to an output of said queue means for receiving said data and/or instructions stored in said queue means and for secondarily storing at least some of said data and/or instructions therein, said at least some of said data and/or instructions stored in said write buffer and control means being stored in said second level cache when said second level cache is not busy and allows the storage of said data and/or instructions therein.

Claim 4

In a multiprocessor system having a plurality of processors including a first processor and at least one second processor, a first level cache connected to each processor, a single second level cache connected to each first level cache and shared by the processors, and a third level main memory connected to the second level cache, a system for queuing and buffering data and/or instructions, comprising: a first level store queue means associated with each processor and having an input connected to its corresponding processor and connected to an input of its corresponding first level cache for receiving said data and/or instructions from said its corresponding processor intended for potential storage in said its corresponding first level cache and for queuing said data and/or instructions therein, each of the first level store queue means having outputs; a plurality of second level store queue means each of which is associated with a first level store queue means and interconnected between the output of such associated first level store queue means and an input of the single second level cache for receiving said data and/or instructions from said first level store queue means and for queuing said data and/or instructions therein prior to storage of said data and/or instruction in said second level cache; and wherein each said second level store queue means comprise a queue means connected to the output of its first level store queue means for receiving said data and/or instructions from said its respective first level store queue means and initially storing said data and/or instructions therein; and write buffer and control means connected to an output of said queue means for receiving said data and/or instructions stored in said queue means and for secondarily storing at least some of said data and/or instructions therein, said at least some of said data and/or instructions stored in said write buffer and control means being stored in said second level cache when said second level cache is not busy and allows the storage of said data and/or instructions therein.

Claim 5

The system of claim 2, wherein said at least some of said data and/or instructions are stored sequentially in said second level cache from said write buffer and control means.

Claim 6

The system of claim 3, wherein certain of said data and/or instructions are allowed write access to said second level cache directly from said queue means.

Claim 7

The system of claim 2, further comprising: addressing means interconnected between each of said second level store queue means and the single shared second level cache for addressing said second level cache, said data and/or instructions stored in a said second level store queue means being stored in said single second level cache in response to the addressing thereof by said addressing means; and buffer means connected to an output of said second level cache for storing said data and/or instructions therein when said data and/or instructions are read out of said second level cache, said data and/or instructions stored in said buffer means of one processor invalidating corresponding obsolete entries of said data and/or instructions in the first level caches of other processors, the invalidation being accomplished before any of said other processors have access to said corresponding obsolete entries of said data and/or instructions.

Claim 8

The system of claim 2, wherein each of the first level store queue means comprise an address field means for storing an absolute address.

Claim 9

In a multiprocessor system having a plurality of processors including a first processor and at least one second processor, a first level cache connected to each processor, a single second level cache connected to each first level cache and shared by the processors, and a third level main memory connected to the second level cache, a system for queuing and buffering data and/or instructions, comprising: a first level store queue means associated with each processor and having an input connected to its corresponding processor and connected to an input of its corresponding first level cache for receiving said data and/or instructions from said its corresponding processor intended for potential storage in said its corresponding first level cache and for queuing said data and/or instructions therein, each of the first level store queue means having outputs and address field means for storing an absolute address; a plurality of second level store queue means each of which is associated with a first level store queue means and interconnected between the output of such associated first level store queue means and an input of the single second level cache for receiving said data and/or instructions from said first level store queue means and for queuing said data and/or instructions therein prior to storage of said data and/or instruction in said second level cache; starting field absolute address register means connected to the address field means of each of said first level store queue means for storing a starting absolute address therein representing an initial absolute address associated with a first of said data and/or instructions to be stored in said first level store queue means; and ending field absolute address register means connected to the address field means of each of said first level store queue means for storing an ending absolute address therein representing the last absolute address associated with a final one of said data and/or instructions to be stored in said first level store queue means.

Claim 10

In a multiprocessor system having a plurality of processors including a first processor and at least one second processor, a first level cache connected to each processor, a single second level cache connected to each first level cache and shared by the processors, and a third level main memory connected to the second level cache, a system for queuing and buffering data and/or instructions, comprising: a first level store queue means associated with each processor and having an input connected to its corresponding processor and connected to an input of its corresponding first level cache for receiving said data and/or instructions from said its corresponding processor intended for potential storage in said its corresponding first level cache and for queuing said data and/or instructions therein, each of the first level store queue means having outputs and address field means for storing an absolute address; a plurality of second level store queue means each of which is associated with a first level store queue means and interconnected between the output of such associated first level store queue means and an input of the single second level cache for receiving said data and/or instructions from said first level store queue means and for queuing said data and/or instructions therein prior to storage of said data and/or instruction in said second level cache; starting field absolute address register means connected to the address field means of each of said first level store queue means for storing a starting absolute address therein representing an initial absolute address associated with a first of said data and/or instructions to be stored in said first level store queue means; and ending field absolute address register means connected to the address field means of each of said first level store queue means for storing an ending absolute address therein representing the last absolute address associated with a final one of said data and/or instructions to be stored in said first level store queue means.

Claim 11

The system of claim 5, wherein each of said queue means of each said second level store queue means comprise: an address field means for storing an absolute address of said data and/or instructions within said second level cache, a data field means for storing said data and/or instructions, and store byte flag field means for storing store byte flags indicative of specific locations at said absolute address within said second level cache wherein said data and/or instructions is stored.

Claim 12

The system of claim 8, wherein each said write buffer and control means further comprises: control means including a plurality of line hold register means connected to the address field means of each of said queue means for storing the absolute address of said data and/or instructions within sad second level cache; a plurality of second level write buffer means interconnected between the data field means of each of said queue means and the shared single second level cache for storing said data and/or instructions therein; and a plurality of store byte flag register means connected to the store byte flag field means of each of said queue means for storing the store byte flags therein indicative of specific locations at said absolute address within said second level cache wherein the obsolete entry of said data and/or instructions is stored.

Claim 13

The system of claim 9, wherein: a directory associated with each of said first level caches of said other processors and with the single second level cache is interrogated using the absolute address stored in one of said line hold register means of said one processor, the corresponding obsolete entries of said data and/or instructions stored in the first level caches of said other processors are invalidated if said absolute address in said one of said line hold register means of said one processor is found in the directories of said first level caches associated with said other processors, and the corresponding obsolete entry of said data and/or instructions stored in the single second level cache is invalidated if said absolute address in said one of said line hold register means of said one processor is found in said directory of said second level cache.

Claim 14

The system of claim 9, wherein said data and/or instructions stored in a said second level write buffer means over-writes the data and/or instructions stored in the specific locations at the absolute address of said second level cache wherein the corresponding obsolete entry of said data and/or instructions is stored, the specific locations being determined and identified in accordance with the store byte flags stored in said store byte flag register means.

Claim 15

In a multiprocessor system including a first processor and at least one second processor where each processor includes an execution unit and a translation lookaside buffer (TLB), a first level cache (L1 cache) connected to each processor, a first level cache directory (L1 cache directory) associated with each said L1 cache, a first level store queue (L1 store queue) connected to each processor and to its said L1 cache, and a second level store queue (L2 store queue) connected to each said L1 store queue, a method of operating said multiprocessor system, comprising the steps of: (a) issuing a first storage request by said execution unit of said first processor, said first storage request including a logical address and a new set of data, said new set of data being associated with a sequential store operation; (b) locating an absolute address in said TLB using said logical address in said first storage request; (c) using said absolute address, searching said L1 cache directory to determine if corresponding data is located at said absolute address of said L1 cache; (d) if said corresponding data is found in said L1 cache, writing said new set of data into said L1 cache at said absolute address and writing said new set of data into said L1 store queue; (e) if said corresponding data is not found in said L1 cache, writing said new set of data into said L1 store queue; and (f) writing said new set of data from said L1 store queue into said L2 store queue; whereby, upon completion of step (a), said first processor may issue a second storage request including a further new set of data and repeat steps (a) through (e) to write said further new set of data into said L1 store queue, said further new set of data being associated with said sequential store operation.

Claim 16

In a multiprocessor system including a first processor and at least one second processor where each processor includes an execution unit and a translation lookaside buffer (TLB), a first level cache (L1 cache) connected to each processor, a first level cache directory (L1 cache directory) associated with each said L1 cache, a first level store queue (L1 store queue) connected to each processor and to its said L1 cache, and a second level store queue (L2 store queue) connected to each said L1 store queue, a method of operating said multiprocessor system, comprising the steps of: (a) issuing a first storage request by said execution unit of said first processor, said first storage request including a logical address and a new set of data, said new set of data being associated with a sequential store operation; (b) locating an absolute address in said TLB using said logical address in said first storage request; (c) using said absolute address, searching said L1 cache directory to determine if corresponding data is located at said absolute address of said L1 cache; (d) if said corresponding data is found in said L1 cache, writing said new set of data into said L1 cache at said absolute address and writing said new set of data into said L1 store queue; (e) if said corresponding data is not found in said L1 cache, writing said new set of data into said L1 store queue; and (f) writing said new set of data from said L1 store queue into said L2 store queue; whereby, upon completion of step (a), said first processor may issue a second storage request including a further new set of data and repeat steps (a) through (e) to write said further new set of data into said L1 store queue, said further new set of data being associated with said sequential store operation.

Claim 17

The method of claim 12, wherein said multiprocessor system further includes at least two second level write buffers (L2 write buffers) connected to each said L2 store queue, and wherein said method further comprises the step of: (g) writing said new set of data associated with said sequential store operation from said L2 store queue associated with said first processor into one of the L2 write buffers, whereby, upon completion of step (g), said further new set of data may be written from said L1 store queue into said L2 store queue.

Claim 18

The method of claim 13, wherein said multiprocessor system further includes a single second level cache (L2 cache) connected to the L2 write buffers of each processor and shared by each processor, a directory associated with said L2 cache (L2 cache directory), and a second level control (L2 control) including an arbitrating means for receiving requests from the processors to access said L2 cache, and wherein said method further comprises the steps of: (h) using said arbitrating means in said L2 control, requesting access to said 1,2 cache; (i) when said access to said L2 cache is granted, searching said L2 cache directory using said absolute address to determine if corresponding obsolete entries of said new set of data are present in said L2 cache; and (j) if an L2 cache hit occurs, writing said new set of data from said one of the L2 write buffers into a location of said L2 cache defined by said absolute address; whereby, said further new set of data may be written from said L2 store queue into another of the L2 write buffers.

Claim 19

The method of claim 14, wherein said multiprocessor system further includes a third level main memory (L3 memory) connected to said L2 cache, and wherein said method further comprises the steps of: (k) if an L2 cache miss occurs, during the writing of said further new set of data from said L2 store queue into said another of the L2 write buffers, inpaging said corresponding obsolete entries of said new set of data from said L3 memory into a location of said L2 cache defined by said absolute address; and (1) following step (k), writing said new set of data from said one of the L2 write buffers into said location of said L2 cache defined by said absolute address.