Command queue apparatus included within a cache unit for facilitating command sequencing

Claim 2

A cache unit for use with a data processing unit for providing fast access to data and instructions fetched from a main store coupled through a system interface to said cache unit in response to commands, each command including a number of words received from said data processing unit, said cache unit comprising: command buffer means coupled to said system interface and to said data processing unit, said command buffer means comprising a plurality of addressable locations for storing the number of words comprising each of a first type of said commands; command queue means coupled to said command buffer means, said command queue means including a buffer having a plurality of multibit locations corresponding in number to at least said plurality of command buffer locations; and, control means coupled to said command queue means and to said command buffer means, said control means being operative in response to a first word of each command to generate signals for loading signals of a first entry into a next available one of said plurality of multibit locations, said entry being coded to identify predetermined characteristics of said command being loaded into a next available one of said plurality of command buffer locations for enabling the storage of a maximum number of said commands at any one time.

Claim 3

The cache unit of claim 1 wherein said first type corresponds to a write command and said predetermined characteristics include the type of command and the number of words included in the command.

Claim 4

The cache unit of claim 2 wherein said entry includes a plurality of bits, a first one of said bits being coded to specify whether said command is read or write, a second one of said bits being coded to specify whether said command is single or double word and third and fourth ones of said bits being coded to specify the address of said next available location within said command buffer means into which said command is to be loaded.

Claim 5

The cache unit of claim 1 wherein said control means being operative upon reciept of each subsequent word of said command to generate signals for loading a corresponding number of subsequent entries into successive locations of said plurality of multibit locations, each subsequent entry being coded to specify only the address of the location within said command buffer means into which said subsequent word is to be loaded for facilitating transfer of said words to said system interface.

Claim 6

The cache unit of claim 2 wherein said commmand buffer means further includes a set of read address terminals coupled to said command queue means and a set of write address terminals and wherein said cache unit further includes: an in pointer register coupled to said set of write address terminals, said in pointer register storing write address signals specifying said address of a next available one of said command buffer locations and said in pointer register being coupled to said control means, said control means generating signals for incrementing by one said write address signals upon writing each entry into said next available one of said multibit locations.

Claim 7

The cache unit of claim 5 wherein said command queue means further includes a plurality of data input terminals, a first number of said data input terminals being coupled to receive signals corresponding to predetermined bits of said first command word identifying said predetermined characteristics and a second number of said data input terminals being coupled to said in pointer register to receive said write address signals specifying the location into which said command word was written, said command queue means being conditioned by said control means to write said predetermined bits and write address signals corresponding to said first entry into said next available one of said plurality of multibit locations.

Claim 8

The cache unit of claim 6 wherein said command queue means further includes: a set of read address terminals; a set of write address terminals; an in pointer address register coupled to said set of write address terminals and to said control means, said in pointer address register storing a write address specifying said next available one of said multibit locations into which an entry is to be written; and, an out pointer address register coupled to said set of read address terminals and to said control means, said out pointer address register storing read address signals specifying an entry to be read out for the transfer of one of said commands; and, said control means generating signals for incrementing by one said write address contents of said in pointer address register each time an entry is written into said command queue means and incrementing by one said read address contents of said out pointer address register each time a word of said command is transferred to said system interface.

Claim 9

The cache unit of claim 1 wherein said cache unit further includes: an in pointer register coupled to said command buffer means and to said command queue means, said in pointer register storing write address signals specifying the command buffer location into which each word of said command word is to be written; and, said control means being operative in response to said first word of said command to generate signals for conditioning said command buffer means for loading said first word of said command into said buffer location specified by said write address signals upon detecting that a predetermined number of said command buffer locations is available for storing commands.

Claim 10

The cache unit of claim 8 wherein said predetermined number of locations corresponds to one of said first type of command having a maximum number of words.

Claim 11

The cache unit of claim 9 wherein said command having said maximum number of words is a write double command.

Claim 12

The cache unit of claim 10 wherein said control means includes: first circuit means coupled to said command queue means for generating signals indicative of the type of command to be transferred from said command buffer means to said system interface; second circuit means coupled to said first circuit means and to said system interface for generating signals indicating the extent to which said command has been processed; and, third circuit means coupled to said data processing unit for receiving signals indicative of when another command has been applied to said command buffer means by said processing unit, said third circuit means being operative in response to said signals from said first and second circuit means to generate an output hold command signal indicating whether or not said predetermined number of said command buffer locations are available.

Claim 13

The cache unit of claim 11 wherein said unit further includes: hold circuit means coupled to said processing unit and to said control means, said hold circuit means being conditioned by a first state of said output hold command signal indicating that said predetermined number of locations are not available, to generate signals for inhibiting said processing unit from generating further commands.

Claim 14

The cache unit of claim 12 wherein said second circuit means includes: a first bistable means being coupled to said processing unit, said first bistable means being switched from a first to a second state in response to signals indicative of receiving said first type of command; and, reset gating means coupled to said command queue means, said system interface and to said first bistable means, said reset gating means generating a reset signal for switching said first bistable means from said second state to said first state upon receiving signals from said command queue means and said interface indicating the transfer of a first word of a write single command to said system interface, said third circuit means being operative upon said first bistable means switching to said first state to switch said hold command signal from said first to a second state signalling the release of said processing unit.

Claim 15

The cache unit of claim 12 wherein said first circuit means includes gating means coupled to said system interface, said gating means being operative to generate an enable write signal indicating a transfer of a second word of said command to said system interface, said first circuit means being operative to condition said third circuit means to switch said hold command signal from said first state to a second state in response to signals indicating that the command words being transferred correspond to a write double command.

Claim 16

The cache unit of claim 14 wherein said unit further includes: a first register coupled to said command buffer means and said control means, said first register for receiving a first word of said command word from said buffer means in response to a signal from said first bistable means indicative of said first state; and, a second register coupled to said command buffer means and to said control means, said second register for receiving a second word of said command from said buffer means in response to said enable write signal.

Claim 17

The cache unit of claim 15 wherein said unit further includes: a selector circuit having first and second sets of input terminals coupled to said first and second registers respectively, a control terminal coupled to said control means and a plurality of output terminals coupled to said system interface, said control means being operative upon receipt of an acceptance response signal from said interface during the transfer of the words of said command to apply an output signal to said control terminal for transferring the second word contents of said second register to said system interface.

Claim 18

The cache unit of claim 12 wherein said command queue means further includes: a set of red address terminals; a set of write address terminals; an in pointer address register coupled to said set of write address terminals and to said control means, said in pointer address register storing a write address specifying said next available one of said multibit locations into which an entry is to be written; an out pointer address register coupled to said set of read address terminals and to said control means, said out pointer address register storing read address signals specifying an entry to be read out for the transfer of one of said commands; and, comparator circuit means coupled to said in pointer address register, to said out pointer address register and to said first circuit means of said control means, said comparator circuit means being operative to generate signals for indicating whether or not there is an identical comparison between said read and write addresses signalling said control means of the presence of a pending command within said command buffer means.

Claim 19

A cache unit for use with a data processing unit for providing fast access to data and instructions fetched from a main store coupled through a system interface to said cache unit in response to commands received from said data processing unit, said cache unit comprising: a plurality of command buffer means, each coupled to said system interface and each comprising a number of addressable locations, one command buffer means for storing a number of words of each first type of command to be transferred to said system interface and another command buffer means for storing each second type of command; command queue means coupled to each of said buffer means, said command queue means comprising a plurality of addressable multibit locations corresponding in number to the sum of said number of locations within said each of said command buffer means; and, control means coupled to said command queue means and to each of said buffer means, said control means being operative in response to a first word, each command of said first and second types to generate signals for writing a first entry into a next available one of said multibit locations, said first entry being coded to include predetermined characteristics of said command being loaded into a next available one of said locations of one of said command buffer means and said control means being operative upon the read out of said first entry to generate signals for transferring said words of said command to said system interface and the loading of a new command within said one buffer when there are a number of locations available to accommodate a predetermined first type of command.

Claim 20

A cache unit for use with a data processing unit for providing fast access to data and instructions fetched from a main store coupled through a system interface to said cache unit in response to commands received from said data processing unit, said cache unit comprising: a plurality of command buffer means, each coupled to said system interface and each comprising a number of addressable locations, one command buffer means for storing a number of words of each first type of command to be transferred to said system interface and another command buffer means for storing each second type of command; command queue means coupled to each of said buffer means, said command queue means comprising a plurality of addressable multibit locations corresponding in number to the sum of said number of locations within said each of said command buffer means; and, control means coupled to said command queue means and to each of said buffer means, said control means being operative in response to a first word, each command of said first and second types to generate signals for writing a first entry into a next available one of said multibit locations, said first entry being coded to include predetermined characteristics of said command being loaded into a next available one of said locations of one of said command buffer means and said control means being operative upon the read out of said first entry to generate signals for transferring said words of said command to said system interface and the loading of a new command within said one buffer when there are a number of locations available to accommodate a predetermined first type of command.

Claim 21

The cache unit of claim 18 wherein said first and second types of command are write and read commands respectively.

Claim 22

The cache unit of claim 19 wherein said first entry includes a plurality of bits, a first one of said bits being coded to specify whether said command is read or write, a second one of said bits being coded to specify whether said command is single or double word and third and fourth ones of said bits being coded to specify the address of said next available location within a corresponding one of said command buffer means into which said command is to be loaded.

Claim 23

The cache unit of claim 20 wherein said control means is operative upon receipt of each subsequent word of first type of command to generate signals for loading a corresponding number of subsequent entries into successive locations of said plurality of multibit locations, each subsequent entry being coded to specify only the address of the location within said corresponding one of said command buffer means into which said subsequent word is to be loaded for facilitating transfer of said words to said system interface.

Claim 24

The cache unit of claim 21 wherein each of said first and second command buffer means further includes a set of read address terminals coupled to said command queue means and a set of write address terminals and wherein said cache unit further includes: a number of in pointer registers, each coupled to said set of write address terminals of a different one of said plurality of command buffer means, each in pointer register storing write address signals specifying said address of a next available one of said command buffer locations and said each in pointer register being coupled to said control means, said control means generating signals for incrementing by one said write address signals upon writing each entry into said next available one of said multibit locations.

Claim 25

The cache unit of claim 22 wherein said command queue means further includes a plurality of data input terminals, a first pair of said data input terminals being coupled to receive signals corresponding to said first and second ones of said bits of said first command word identifying said characteristics and a second pair of said data input terminals being coupled to each of said in pointer registers to receive said write address signals specifying the location into which said command word was written, said command queue means being conditioned by said control means to write said first and second ones of said bits and write address signals corresponding to said first entry into said next available one of said plurality of multibit locations.

Claim 26

The cache unit of claim 23 wherein said command queue means further includes: a set of read address terminals; a wet of write address terminals; an in pointer address register coupled to said set of write address terminals and to said control means, said in pointer address register storing a write address specifying said next available one of said multibit locations into which an entry is to be written; an out pointer address register coupled to said set of read address terminals and to said control means, said out pointer address register storing read address signals specifying an entry to be read out for the transfer of one of said commands; and, said control means generating signals for incrementing by one said write address contents of said in pointer address register each time an entry is written into said command queue means and incrementing by one said read address contents of said out pointer address register each time a word of said first or second type of command is transferred to said system interface.

Claim 27

The cache unit of claim 18 wherein said control means includes: first circuit means coupled to said command queue means for generating signals indicative of the type of command to be transferred from each of said plurality of said command buffer means to said system interface; second circuit means coupled to said first circuit means and to said system interface for generating signals indicating the extent to which said command has been processed; and, third circuit means coupled to said data processing unit for receiving signals indicating of when another command has been applied to said command buffer means by said processing unit, said third circuit means being operative in response to said signals from said first and second circuit means to generate an output hold command signal indicating whether or not said predetermined number of said command buffer locations are available.

Claim 28

The cache unit of claim 25 wherein said unit further includes: hold circuit means coupled to said processing unit and to said control means, said hold circuit means being conditioned by a first state of said output hold command signal indicating that said predetermined number of locations are not available, to generate signals for inhibiting said processing unit from generating further commands.

Claim 29

The cache unit of claim 25 wherein said second circuit means includes: a first bistable means being coupled to said processing unit, said first bistable means being switched from a first to a second state in response to signals indicative of receiving said first type of command; and, reset gating means coupled to said command queue means, said system interface and to said first bistable means, said reset gating means generating a reset signal for switching said first bistable means from said second state to said first state upon receiving signals from said command queue means and said interface indicating the transfer of a first word of a write single command to said system interface, said third circuit means being operative upon said first bistable means switching to said first state to switch said hold command signal from said first to a second state signalling the release of said processing unit.

Claim 30

The cache unit of claim 26 wherein said first circuit means includes gating means coupled to said system interface, said gating means being operative to generate an enable write signal indicating a transfer of a second word of said first type of command to said system interface, said first circuit means being operative to condition said third circuit means to switch said hold command signal from said first state to a second state in response to signals indicating that the command words being transferred correspond to a write double command.

Claim 31

The cache unit of claim 27 wherein said unit further includes: a first register coupled to each of said command buffer means and said control means, said first register for receiving a first word of said first and second types of commands from a corresponding one of said buffer means in response to a signal from said first bistable means indicative of said first state; and, a second register coupled to a predetermined one of said command buffer means and to said control means, said second register for receiving a second word of said first type of command from said predetermined one of said buffer means in response to said enable write signal.

Claim 32

The cache unit of claim 28 wherein said unit further includes: a selector circuit having first and second sets of input terminals coupled to said first and second registers respectively, a control terminal coupled to said control means and a plurality of output terminals coupled to said system interface, said control means being operative upon receipt of an acceptance response signal from said interface during the transfer of the words of said first type of command to apply an output signal to said control terminal for transferring the second word contents of said second register to said system interface.

Claim 33

The cache unit of claim 26 wherein said command queue means further includes: a set of read address terminals; a set of write address terminals; an in pointer address register coupled to said set of write address terminals and to control means, said in pointer address register storing a write address specifying said next available one of said multibit locations into which an entry is to be written; an out pointer address register coupled to said set of read address terminals and to said control means, said out pointer address register storing read address signals specifying an entry to be read out for the transfer of one of said commands; and, comparator circuit means coupled to said in pointer address register, to said out pointer address register and to said first circuit means of said control means, said comparator circuit means being operative to generate signals for indicating whether or not there is an indentical comparison between said read and write addresses signalling said control means of the presence of a pending command within one of said command buffer means.

Claim 34

A cache system for use with a data processing unit for providing fast access to data and instructions fetched from a main store coupled through a system interface to said cache system in response to commands received from said data processing unit, each write type command including a command word and a number of data words, said cache system comprising: a first register coupled to said system interface for transferring said command word of each write type command; a second register coupled to said system interface for transferring said data words of each write type command; an addressable write command buffer coupled to said first and second registers and to said data processing unit, said write command buffer including a plurality of locations for storing said command and data words of said each write type command to be transferred to said system interface; and addressable command queue coupled to said write command buffer, said command queue including a plurality of multibit locations; and, control means coupled to said command queue, said processing unit, said first and second registers and to said write buffer, said control means being operative in response to each command word to generate signals for writing an entry having a predetermined format into a next available one of said plurality of multibit locations, a first one of said entry being coded to identify the type and number of words in addition to the location within said write buffer into which said command word is to be loaded and said control means in response to said entry read out from said command queue being operative to generate signals to transfer said command word to said first register, a first data word to said second register and the loading of a new command into said write buffer in accordance with the progress of said transfer upon detecting the availability of a predetermined number of locations therein.

Claim 35

A cache system for use with a data processing unit for providing fast access to data and instructions fetched from a main store coupled through a system interface to said cache system in response to commands received from said data processing unit, each write type command including a command word and a number of data words, said cache system comprising: a first register coupled to said system interface for transferring said command word of each write type command; a second register coupled to said system interface for transferring said data words of each write type command; an addressable write command buffer coupled to said first and second registers and to said data processing unit, said write command buffer including a plurality of locations for storing said command and data words of said each write type command to be transferred to said system interface; and addressable command queue coupled to said write command buffer, said command queue including a plurality of multibit locations; and, control means coupled to said command queue, said processing unit, said first and second registers and to said write buffer, said control means being operative in response to each command word to generate signals for writing an entry having a predetermined format into a next available one of said plurality of multibit locations, a first one of said entry being coded to identify the type and number of words in addition to the location within said write buffer into which said command word is to be loaded and said control means in response to said entry read out from said command queue being operative to generate signals to transfer said command word to said first register, a first data word to said second register and the loading of a new command into said write buffer in accordance with the progress of said transfer upon detecting the availability of a predetermined number of locations therein.

Claim 36

The cache system of claim 32 wherein said first one of said entries includes a plurality of bits, a first one of said bits being coded to specify whether said command is read or write, a second one of said bits being coded to specify whether said command is single or double word and third and fourth ones of said bits being coded to specify the address of said next available location within said write command buffer into which said command word is to be loaded.

Claim 37

The cache system of claim 33 wherein said control means is operative upon receipt of each subsequent word of said write command to generate signals for loading a corresponding number of subsequent entries into successive locations of said plurality of multibit locations, each subsequent entry being coded to specify only the address of the locations within said write command buffer into which said subsequent word is to be loaded for facilitating transfer of said words to said second register.

Claim 38

The cache system of claim 34 wherein said command queue further includes: a set of read address terminals; a set of write address terminals; an in pointer address register coupled to said set of write address terminals and to said control means, said in pointer address register storing a write address specifying said next available one of said multibit locations into which an entry is to be written; an out pointer address register coupled to said set of read address terminals and to said control means, said out pointer address register storing read address signals specifying an entry to be read out for the transfer of one of said words of write command; and, said control means generating signals for incrementing by one write address contents of said in pointer address register each time an entry is written into said command queue and incrementing by one said read address contents of said out pointer address register each time a word of said command is transferred to said first and second registers.

Claim 39

The cache system of claim 35 wherein said control means includes: first circuit means coupled to said command queue for generating signals indicative of the type of command to be transferred from said command buffer to said system interface; second circuit means coupled to said first circuit means and to said system interface for generating signals indicating the extent to which said write command has been processed; and, third circuit means coupled to said data processing unit for receiving signals indicative of when another command has been applied to said command buffer by said processing unit, said third circuit means being operative in response to said signals from said first and second circuit means to generate an output hold command signal indicating whether or not said predetermined number of said command buffer locations are available.

Claim 40

The cache system of claim 36 wherein said unit further includes: hold circuit means coupled to said processing unit and to said control means, said hold circuit means being conditioned by a first state of said output hold command signal indicating that said predetermined number of locations are not available, to generate signals for inhibiting said processing unit from generating further commands.

Claim 41

The cache system of claim 37 wherein said second circuit means includes: a first bistable means being coupled to said processing unit, said first bistable means being switched from a first to a second state in response to signals indicative of receiving said write command; and, reset gating means coupled to said command queue means, said system interface and to said first bistable means, said reset gating means generating a reset signal for switching said first bistable means from said second state to said first state upon receiving signals from said command queue and said interface indicating the transfer of a first word of a write single command to said first register, said third circuit means being operative upon said first bistable means switching to said first state to switch said hold command signal from said first to a second state signalling the release of said processing unit.

Claim 42

The cache system of claim 38 wherein said first circuit means includes gating means coupled to said second register, said gating means being operative to generate an enable write signal indicating a transfer of a second word of said command to said second register, said first circuit means being operative to condition said third circuit means to switch said hold command signal from said first state to a second state in response to signals indicating that the command words being transferred correspond to a write double command.

Claim 43

The cache system of claim 39 wherein said system further includes: a selector circuit having first and second sets of input terminals coupled to said first and second registers respectively, a control terminal coupled to said control means and a plurality of output terminals coupled to said system interface, said control means being operative upon receipt of an acceptance response signal from said system interface during the transfer of the words of said write command to apply an output signal to said control terminal for transferring the second word contents of said second register to said system interface.

Claim 44

The cache system of claim 37 wherein said command queue further includes: a set of read address terminals; a set of write address terminals; an in pointer address register coupled to said set of write address terminals and to said control means, said in pointer address register storing a write address specifying said next available one of said multibit locations into which an entry is to be written; an out pointer address register coupled to said set of read address terminals and to said control means, said out pointer address register storing read address signals specifying an entry to be read out for the transfer of one of said commands; and, comparator circuit means coupled to said in pointer address register, to said out pointer address register and to said first circuit means of said control means, said comparator circuit means being operative to generate signals for indicating whether or not there is an identical comparison between said read and write address signalling said control means of the presence of a pending command within said write command buffer