US5614427A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of making an array of TFTs having reduced parasitic capacitance
Assignee: Innolux Corp
•
Filing: 1995-01-20
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Granted: 1997-03-25
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Expires: 2015-01-20
Abstract
Abstract A thin film transistor (TFT) array in an active matrix liquid crystal display (AMLCD) including a centrally located round source electrode completely surrounded by a substantially annular or circular shaped drain electrode. The geometric design of the TFT of this invention provides for a thin film transistor having a reduced parasitic capacitance and decreased photosensitivity. The TFTs of this invention are located at the intersections of gate and drain lines of an active matrix LCD array thereby increasing the size of the pixel display openings of the matrix array.
Inventors
- 👤 Willem den Boer
- 👤 Mohshi Yang
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 03:08
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/67; H10D30/6757; G; G02; G02F; G02F1/00; G02F1/01; G02F1/13; G02F1/133; G02F1/136; G02F1/1362; G02F1/1368; H10D30/6729; H10D30/673; H10D30/674; H10D86/00
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
137 words
A method of making an array of thin film transistors corresponding to an array of electrode members, the method comprising the steps of: a) depositing a gate electrode layer on a substrate; b) depositing a semiconductor film over said gate electrode layer; c) depositing a metal layer over said semiconductor layer; d) patterning said metal layer of step c) so as to form source and drain electrodes for each thin film transistor in the array wherein the source electrode of each transistor is completely surrounded by the drain electrode so that the thin film transistors in the array have reduced parasitic capacitances; and e) depositing and patterning an electrode layer on top of said source and drain electrodes so that a substantial portion of the electrode member corresponding to each thin film transistor is laterally spaced therefrom.
Claim 2
Independent Claim
137 words
A method of making an array of thin film transistors corresponding to an array of electrode members, the method comprising the steps of: a) depositing a gate electrode layer on a substrate; b) depositing a semiconductor film over said gate electrode layer; c) depositing a metal layer over said semiconductor layer; d) patterning said metal layer of step c) so as to form source and drain electrodes for each thin film transistor in the array wherein the source electrode of each transistor is completely surrounded by the drain electrode so that the thin film transistors in the array have reduced parasitic capacitances; and e) depositing and patterning an electrode layer on top of said source and drain electrodes so that a substantial portion of the electrode member corresponding to each thin film transistor is laterally spaced therefrom.
Claim 3
Independent Claim
174 words
A method of making an array of a-Si TFTs comprising the steps of: providing a substrate; forming a plurality of gate electrodes on the substrate; forming a gate insulating layer over the gate electrodes on the substrate; depositing an a-Si semiconductor layer over the gate insulating layer on the substrate; patterning the a-Si semiconductor layer so that it remains in an array of TFT areas; forming a source and drain electrode in each said TFT area in the array so that the drain electrode completely surrounds the source electrode laterally in each resulting TFT; depositing an insulating layer on the substrate over at least the drain electrodes of the TFTs in the array; and forming and patterning a plurality of pixel electrodes on the substrate so that each of the pixel electrodes is connected to a source electrode of a corresponding TFT by way of an electrode portion which crosses over the drain electrode of the TFT, with the electrode portion being insulated from the drain in the crossover area by the insulating layer.
Claim 4
Independent Claim
174 words
A method of making an array of a-Si TFTs comprising the steps of: providing a substrate; forming a plurality of gate electrodes on the substrate; forming a gate insulating layer over the gate electrodes on the substrate; depositing an a-Si semiconductor layer over the gate insulating layer on the substrate; patterning the a-Si semiconductor layer so that it remains in an array of TFT areas; forming a source and drain electrode in each said TFT area in the array so that the drain electrode completely surrounds the source electrode laterally in each resulting TFT; depositing an insulating layer on the substrate over at least the drain electrodes of the TFTs in the array; and forming and patterning a plurality of pixel electrodes on the substrate so that each of the pixel electrodes is connected to a source electrode of a corresponding TFT by way of an electrode portion which crosses over the drain electrode of the TFT, with the electrode portion being insulated from the drain in the crossover area by the insulating layer.
Claim 5
Independent Claim
145 words
A method of making an LCD including an array of TFTs having reduced parasitic capacitance, the method comprising the steps of: providing a first substrate; forming a plurality of gate electrodes on the first substrate; forming an insulating layer on the first substrate adjacent the gate electrodes; depositing and patterning a semiconductor layer so that it remains in a plurality of TFT areas; forming a source electrode on top of the semiconductor layer in each of the TFT areas; forming a drain electrode completely surrounding the source electrode in each of the TFT areas; forming a plurality of pixel electrodes, each being connected to the source electrode of a corresponding TFT, a substantial portion of each pixel electrode being laterally spaced from its corresponding TFT; providing a second substrate; and sandwiching a liquid crystal layer between the first and second substrates thereby forming the LCD.
Claim 6
Independent Claim
145 words
A method of making an LCD including an array of TFTs having reduced parasitic capacitance, the method comprising the steps of: providing a first substrate; forming a plurality of gate electrodes on the first substrate; forming an insulating layer on the first substrate adjacent the gate electrodes; depositing and patterning a semiconductor layer so that it remains in a plurality of TFT areas; forming a source electrode on top of the semiconductor layer in each of the TFT areas; forming a drain electrode completely surrounding the source electrode in each of the TFT areas; forming a plurality of pixel electrodes, each being connected to the source electrode of a corresponding TFT, a substantial portion of each pixel electrode being laterally spaced from its corresponding TFT; providing a second substrate; and sandwiching a liquid crystal layer between the first and second substrates thereby forming the LCD.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-03-24 | 2000-09-23 | 2001-03-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-03-24 | 2004-09-23 | 2005-03-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-03-24 | 2008-09-23 | 2009-03-25 | $7700.00 | Window Closed / Lapsed |