Method of forming vertical gate thin film transistors in liquid crystal array

Claim 1

A method of producing an integrated array of liquid crystal pixels and vertical gate thin film transistors for charging said pixels and comprising the steps of: providing an insulating substrate at least as large as the desired array; forming on said substrate a first layer of a transparent conductive material and a second layer of a semiconducting material; defining and etching said first and second layers to form one element of each said liquid crystal pixel with an overlay of semiconducting material, said pixel elements being arranged in a plurality of rows and columns; forming over said substrate and said previously formed elements a third layer, a fourth layer of a semiconducting material, and a fifth layer of a conducting material; defining and etching said second, third, fourth and fifth layers to provide on each said pixel element a first element for each said transistor formed from said second layer, and a first set of narrow lines from said third, fourth and fifth layers, each said narrow line traversing a column of said first transistor elements, each portion of said fifth layer subjacent one of said first transistor elements providing a second transistor element; forming over said substrate and said previously formed elements a sixth layer of at least an insulating material; defining and etching said sixth layer to form insulating areas, each area traversing one of said second transistor elements; forming over said substrate and said previously formed elements a seventh layer of a conductive material insulated from said previously formed elements by said insulating area; defining and etching said seventh layer to form a second set of narrow lines, each said line traversing a row of said second transistor elements, each portion of said second set of narrow lines adjacent the edges of a set of first and second transistor elements forming a third element of the respective transistor, and wherein each said pixel element has an extended portion and said transistor elements are positioned one the respective extended portions.

Claim 2

A method of producing an integrated array of liquid crystal pixels and vertical gate thin film transistors for charging said pixels and comprising the steps of: providing an insulating substrate at least as large as the desired array; forming on said substrate a first layer of a transparent conductive material and a second layer of a semiconducting material; defining and etching said first and second layers to form one element of each said liquid crystal pixel with an overlay of semiconducting material, said pixel elements being arranged in a plurality of rows and columns; forming over said substrate and said previously formed elements a third layer, a fourth layer of a semiconducting material, and a fifth layer of a conducting material; defining and etching said second, third, fourth and fifth layers to provide on each said pixel element a first element for each said transistor formed from said second layer, and a first set of narrow lines from said third, fourth and fifth layers, each said narrow line traversing a column of said first transistor elements, each portion of said fifth layer subjacent one of said first transistor elements providing a second transistor element; forming over said substrate and said previously formed elements a sixth layer of at least an insulating material; defining and etching said sixth layer to form insulating areas, each area traversing one of said second transistor elements; forming over said substrate and said previously formed elements a seventh layer of a conductive material insulated from said previously formed elements by said insulating area; defining and etching said seventh layer to form a second set of narrow lines, each said line traversing a row of said second transistor elements, each portion of said second set of narrow lines adjacent the edges of a set of first and second transistor elements forming a third element of the respective transistor, and wherein each said pixel element has an extended portion and said transistor elements are positioned one the respective extended portions.

Claim 20

A method of producing an integrated array of liquid crystal pixels and vertical gate thin film transistors for charging said pixels and comprising the steps of: providing an insulating substrate at least as large as the desired array; forming on said substrate a first layer of a transparent conductive material and a second layer of a semiconducting material; defining and etching said first and second layers to form one element of each said liquid crystal pixel with an overlay of semiconducting material, said pixel elements being arranged in a plurality of rows an columns; forming over said substrate and said previously formed elements a third layer, a fourth layer of a semiconducting material, and a fifth layer of a conducting material, said fifth layer being composed of one of the group consisting of tungsten, tantalum and nichrome; defining and etching said second, third, fourth and fifth layers to provide on each said pixel element a first element for each said transistor formed from said second layer, and a first set of narrow lines from said third, fourth and fifth layers, each said narrow line traversing a column of said first transistor elements, each port ion of said fifth layer superjacent one of said first transistor elements providing a second transistor element; forming over said substrate and said previously formed elements a sixth layer of an least an insulating material; defining and etching said sixth layer to form insulating area, each area traversing one of said second transistor elements; forming over said substrate and said previously formed elements a seventh layer of a conductive material insulated from said previously formed elements by said insulating area; and defining and etching said seventh layer to form a second set of narrow lines, each said line traversing a row of said second transistor elements, each portion of said second set of narrow lines adjacent the edges of a set of first and second transistor elements forming a third element of the respective transistor.

Claim 21

A method of producing an integrated array of liquid crystal pixels and vertical gate thin film transistors for charging said pixels and comprising the steps of: providing an insulating substrate at least as large as the desired array; forming on said substrate a first layer of a transparent conductive material and a second layer of a semiconducting material; defining and etching said first and second layers to form one element of each said liquid crystal pixel with an overlay of semiconducting material, said pixel elements being arranged in a plurality of rows an columns; forming over said substrate and said previously formed elements a third layer, a fourth layer of a semiconducting material, and a fifth layer of a conducting material, said fifth layer being composed of one of the group consisting of tungsten, tantalum and nichrome; defining and etching said second, third, fourth and fifth layers to provide on each said pixel element a first element for each said transistor formed from said second layer, and a first set of narrow lines from said third, fourth and fifth layers, each said narrow line traversing a column of said first transistor elements, each port ion of said fifth layer superjacent one of said first transistor elements providing a second transistor element; forming over said substrate and said previously formed elements a sixth layer of an least an insulating material; defining and etching said sixth layer to form insulating area, each area traversing one of said second transistor elements; forming over said substrate and said previously formed elements a seventh layer of a conductive material insulated from said previously formed elements by said insulating area; and defining and etching said seventh layer to form a second set of narrow lines, each said line traversing a row of said second transistor elements, each portion of said second set of narrow lines adjacent the edges of a set of first and second transistor elements forming a third element of the respective transistor.

Claim 22

A method of producing an integrated array of liquid crystal pixels and vertical gate thin film transistors for charging said pixels and comprising the steps of: providing an insulating substrate at least as large as the desired array; forming on said substrate one element of each said liquid crystal pixel, said pixel elements being comprised of a transparent, conductive material and arranged in a plurality of rows and columns; forming on said substrate, and over a part of each said pixel element, a first element of one of said transistors; forming on said substrate, and over and insulated from each said first transistor element, a second transistor element, the second transistor elements on one row of said pixel elements being coupled together; and forming on said substrate, adjacent edges of and insulated from each set of said first and second transistor elements, a third transistor element, the third transistor elements on one column of said pixel elements being coupled together; wherein said array further includes peripheral circuitry including additional integrated vertical gate thin film transistors and wherein the steps of forming an element of each of said pixels further includes simultaneously forming crossunder areas for connecting portions of said circuitry.

Claim 23

A method of producing an integrated array of liquid crystal pixels and vertical gate thin film transistors for charging said pixels and comprising the steps of: providing an insulating substrate at least as large as the desired array; forming on said substrate one element of each said liquid crystal pixel, said pixel elements being comprised of a transparent, conductive material and arranged in a plurality of rows and columns; forming on said substrate, and over a part of each said pixel element, a first element of one of said transistors; forming on said substrate, and over and insulated from each said first transistor element, a second transistor element, the second transistor elements on one row of said pixel elements being coupled together; and forming on said substrate, adjacent edges of and insulated from each set of said first and second transistor elements, a third transistor element, the third transistor elements on one column of said pixel elements being coupled together; wherein said array further includes peripheral circuitry including additional integrated vertical gate thin film transistors and wherein the steps of forming an element of each of said pixels further includes simultaneously forming crossunder areas for connecting portions of said circuitry.

Claim 24

A method of producing an integrated array of liquid crystal pixels and vertical gate thin film transistors for charging said pixels and comprising the steps of: providing an insulating substrate at least as large as the desired array; forming on said substrate one element of each said liquid crystal pixel, said pixel elements being comprised of a transparent, conductive material and arranged in a plurality of rows and columns; forming on said substrate, and over a part of each said pixel element, a first element of one of said transistors; forming on said substrate, and over and insulated from each said first transistor element, a second transistor element, the second transistor elements on one row of said pixel elements being coupled together; and forming on said substrate, adjacent edges of and insulated from each set of said first and second transistor elements, a third transistor element, the third transistor elements on one column of said pixel elements being coupled together; wherein said array further includes peripheral circuitry including additional integrated vertical gate thin film transistors and wherein the steps of forming an element of each of said pixels further includes simultaneously forming interconnecting portions of said circuitry.

Claim 25

A method of producing an integrated array of liquid crystal pixels and vertical gate thin film transistors for charging said pixels and comprising the steps of: providing an insulating substrate at least as large as the desired array; forming on said substrate one element of each said liquid crystal pixel, said pixel elements being comprised of a transparent, conductive material and arranged in a plurality of rows and columns; forming on said substrate, and over a part of each said pixel element, a first element of one of said transistors; forming on said substrate, and over and insulated from each said first transistor element, a second transistor element, the second transistor elements on one row of said pixel elements being coupled together; and forming on said substrate, adjacent edges of and insulated from each set of said first and second transistor elements, a third transistor element, the third transistor elements on one column of said pixel elements being coupled together; wherein said array further includes peripheral circuitry including additional integrated vertical gate thin film transistors and wherein the steps of forming an element of each of said pixels further includes simultaneously forming interconnecting portions of said circuitry.

Claim 26

A method of producing an integrated array of liquid crystal pixels and vertical gate thin film transistors for charging said pixels and comprising the steps of: providing an insulating substrate at least as large as the desired array; forming on said substrate one element of each said liquid crystal pixel, said pixel elements being comprised of a transparent, conductive material and arranged in a plurality of rows and columns; forming on said substrate, and over a part of each said pixel element, a first element of one of said transistors; forming on said substrate, and over and insulated from each said first transistor element, a second transistor element, the second transistor elements on one row of said pixel elements being coupled together; and forming on said substrate, adjacent edges of and insulated from each set of said first and second transistor elements, a third transistor element, the third transistor elements on one column of said pixel elements being coupled together; wherein said array further includes peripheral circuitry including additional integrated vertical gate thin film transistors and wherein the steps of forming said first and second elements of said charging transistors further includes simultaneously forming at least two elements of said additional thin film transistors.

Claim 27

A method of producing an integrated array of liquid crystal pixels and vertical gate thin film transistors for charging said pixels and comprising the steps of: providing an insulating substrate at least as large as the desired array; forming on said substrate one element of each said liquid crystal pixel, said pixel elements being comprised of a transparent, conductive material and arranged in a plurality of rows and columns; forming on said substrate, and over a part of each said pixel element, a first element of one of said transistors; forming on said substrate, and over and insulated from each said first transistor element, a second transistor element, the second transistor elements on one row of said pixel elements being coupled together; and forming on said substrate, adjacent edges of and insulated from each set of said first and second transistor elements, a third transistor element, the third transistor elements on one column of said pixel elements being coupled together; wherein said array further includes peripheral circuitry including additional integrated vertical gate thin film transistors and wherein the steps of forming said first and second elements of said charging transistors further includes simultaneously forming at least two elements of said additional thin film transistors.

Claim 28

A method of producing an integrated array of liquid crystal pixels and vertical gate thin film transistors for charging said pixels and comprising the steps of: providing an insulating substrate at least as large as the desired array; forming on said substrate one element of each said liquid crystal pixel, said pixel elements being comprised of a transparent, conductive material and arranged in a plurality of rows and columns; forming on said substrate, and over a part of each said pixel element, a first element of one of said transistors; forming on said substrate, and over and insulated from each said first transistor element, a second transistor element, the second transistor elements on one row of said pixel elements being coupled together; and forming on said substrate, adjacent edges of and insulated from each set of said first and second transistor elements, a third transistor element, the third transistor elements on one column of said pixel elements being coupled together; wherein said array further includes peripheral circuitry including additional integrated vertical gate thin film transistors and wherein the steps of forming said third elements of said charging transistors further includes simultaneously forming at least one element of each of the transistors of the peripheral circuitry.

Claim 29

A method of producing an integrated array of liquid crystal pixels and vertical gate thin film transistors for charging said pixels and comprising the steps of: providing an insulating substrate at least as large as the desired array; forming on said substrate one element of each said liquid crystal pixel, said pixel elements being comprised of a transparent, conductive material and arranged in a plurality of rows and columns; forming on said substrate, and over a part of each said pixel element, a first element of one of said transistors; forming on said substrate, and over and insulated from each said first transistor element, a second transistor element, the second transistor elements on one row of said pixel elements being coupled together; and forming on said substrate, adjacent edges of and insulated from each set of said first and second transistor elements, a third transistor element, the third transistor elements on one column of said pixel elements being coupled together; wherein said array further includes peripheral circuitry including additional integrated vertical gate thin film transistors and wherein the steps of forming said third elements of said charging transistors further includes simultaneously forming at least one element of each of the transistors of the peripheral circuitry.

Claim 30

A method of producing an integrated array of liquid crystal pixels and vertical gate thin film transistors for charging said pixels and comprising the steps of: providing an insulating substrate at least as large as the desired array; forming on said substrate one element of each said liquid crystal pixel, said pixel elements being comprised of a transparent, conductive material and arranged in a plurality of rows and columns; forming on said substrate, and over a part of each said pixel element, a first element of one of said transistors; forming on said substrate, and over and insulated from each said first transistor element, a second transistor element, the second transistor elements on one row of said pixel elements being coupled together; and forming of said substrate, adjacent edges of and insulated from each set of said first and second transistor elements, a third transistor element, the third transistor elements on one column of said pixel elements being coupled together; wherein said array further includes peripheral circuitry including additional integrated vertical gate thin film transistors and wherein the steps of forming said third elements of said charging transistors further includes simultaneously forming portions of interconnecting lines for the peripheral circuitry.

Claim 31

A method of producing an integrated array of liquid crystal pixels and vertical gate thin film transistors for charging said pixels and comprising the steps of: providing an insulating substrate at least as large as the desired array; forming on said substrate one element of each said liquid crystal pixel, said pixel elements being comprised of a transparent, conductive material and arranged in a plurality of rows and columns; forming on said substrate, and over a part of each said pixel element, a first element of one of said transistors; forming on said substrate, and over and insulated from each said first transistor element, a second transistor element, the second transistor elements on one row of said pixel elements being coupled together; and forming of said substrate, adjacent edges of and insulated from each set of said first and second transistor elements, a third transistor element, the third transistor elements on one column of said pixel elements being coupled together; wherein said array further includes peripheral circuitry including additional integrated vertical gate thin film transistors and wherein the steps of forming said third elements of said charging transistors further includes simultaneously forming portions of interconnecting lines for the peripheral circuitry.

Claim 32

A method of producing an integrated array of liquid crystal pixels and vertical gate thin film transistors for charging said pixels and comprising the steps of: providing an insulating substrate at least as large as the desired array; forming on said substrate one element of each said liquid crystal pixel, said pixel elements being comprised of a transparent, conductive material and arranged in a plurality of rows and columns; forming on said substrate, and over a part of each said pixel element, a first element of one of said transistors; forming on said substrate, and over and insulated from each said first transistor element, a second transistor element, the second transistor elements on one row of said pixel element being coupled together; and forming on said substrate, adjacent edges of and insulated from each set of said first and second transistor elements, a third transistor element, the third transistor elements on one column of said pixel elements being coupled together; wherein said array further includes peripheral circuitry including additional integrated vertical gate thin film transistors and wherein the step of forming and insulating said second and third elements of said charging transistors further includes simultaneously forming insulating areas over at least the first and second elements of said additional transistors.

Claim 33

A method of producing an integrated array of liquid crystal pixels and vertical gate thin film transistors for charging said pixels and comprising the steps of: providing an insulating substrate at least as large as the desired array; forming on said substrate one element of each said liquid crystal pixel, said pixel elements being comprised of a transparent, conductive material and arranged in a plurality of rows and columns; forming on said substrate, and over a part of each said pixel element, a first element of one of said transistors; forming on said substrate, and over and insulated from each said first transistor element, a second transistor element, the second transistor elements on one row of said pixel element being coupled together; and forming on said substrate, adjacent edges of and insulated from each set of said first and second transistor elements, a third transistor element, the third transistor elements on one column of said pixel elements being coupled together; wherein said array further includes peripheral circuitry including additional integrated vertical gate thin film transistors and wherein the step of forming and insulating said second and third elements of said charging transistors further includes simultaneously forming insulating areas over at least the first and second elements of said additional transistors.