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US5605855A
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Process for fabricating a graded-channel MOS device
Assignee: Motorola Solutions Inc
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Filing: 1995-02-28
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Granted: 1997-02-25
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Expires: 2015-02-28
Abstract
Abstract A process for fabricating a graded-channel MOS device includes the formation of a masking layer (16) on the surface of a semiconductor substrate (10) and separated from the surface by a gate oxide layer (12). A first doped region (22) is formed in a channel region (20) of the semiconductor substrate (10) using the masking layer (16) as a doping mask. A second doped region (24) is formed in the channel region (20) and extends from the principal surface (14) of the semiconductor substrate (10) to the first doped region (22). A gate electrode (34) is formed within an opening (18) in the masking layer (16) and aligned to the channel region (20). Upon removal of the masking layer (16) source and drain regions (36, 38) are formed in the semiconductor substrate (10) and aligned to the gate electrode (34).
Inventors
- 👤 Ko-Min Chang
- 👤 Marius Orlowski
- 👤 Craig Swift
- 👤 Shih-Wei Sun
- 👤 Shiang-Chyong Luo
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 19:18
CPC Classifications
H; H10; H10P; H10P30/00; H10P30/20; H10P30/202; H10P30/204; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0217; H10D30/0223; H10D30/0225; H10D62/00; H10D62/10; H10D62/17; H10D62/213; H10D62/221; H10D62/235; H10D62/299; H10D62/307; H10D62/351; H10D62/357; H10D62/364; H10D62/371; H10D64/00; H10D64/01; H10D64/018; H10P30/21; H10P30/212
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
147 words
A process for fabricating a semiconductor device comprising the steps of: providing a semiconductor substrate of a first conductivity type having a surface; defining a channel region in the semiconductor substrate; forming a first doped region of the first conductivity type in the channel region; forming a second doped region of the first conductivity type in the channel region, wherein: the second doped region extends from the surface to the first doped region and separates the first doped region from the surface; the second doped region is narrower in cross-sectional width than the first doped region; and the steps of forming the first doped region and forming the second doped region are performed during separate processing steps; forming a gate electrode overlying the channel region; and forming source and drain regions of a second conductivity type in the semiconductor substrate on either side of the gate electrode.
Claim 2
Dependent Claim
147 words
A process for fabricating a semiconductor device comprising the steps of: providing a semiconductor substrate of a first conductivity type having a surface; defining a channel region in the semiconductor substrate; forming a first doped region of the first conductivity type in the channel region; forming a second doped region of the first conductivity type in the channel region, wherein: the second doped region extends from the surface to the first doped region and separates the first doped region from the surface; the second doped region is narrower in cross-sectional width than the first doped region; and the steps of forming the first doped region and forming the second doped region are performed during separate processing steps; forming a gate electrode overlying the channel region; and forming source and drain regions of a second conductivity type in the semiconductor substrate on either side of the gate electrode.
Claim 3
Dependent Claim
74 words
The process of claim 1, wherein the step of forming a gate electrode comprises the steps of: providing a masking layer overlying the surface, the masking layer having an opening therein exposing the channel region; depositing a first semiconductor layer overlying the masking layer and the channel region; depositing a second semiconductor layer overlying the first semiconductor layer; and removing a portion of the first and second semiconductor layers to form a planar surface.
Claim 4
Dependent Claim
29 words
The process of claim 2, wherein the step of forming the second doped region comprises ion implantation through the first semiconductor layer prior to depositing the second semiconductor layer.
Claim 5
Dependent Claim
83 words
The process of claim 1 wherein the step of forming a gate electrode comprises the steps of: providing a masking layer overlying the surface, the masking layer having an opening therein exposing the channel region; depositing a first semiconductor layer overlying the masking layer and the channel region; etching the first semiconductor layer to form sidewall spacers in the opening; depositing a second semiconductor layer overlying the sidewall spacers; and removing a portion of the second semiconductor layer to form a planar surface.
Claim 6
Dependent Claim
64 words
The process of claim 1, further comprising steps of: providing a masking layer overlying the surface, the masking layer having an opening therein exposing the channel region; and forming sidewall spacers within the opening prior to the step of forming the second doped region, wherein the step of forming a second doped region comprises ion implantation using the sidewall spacers as an implantation mask.
Claim 7
Dependent Claim
39 words
The process of claim 1, wherein the second doped region is spaced apart from the source and drain regions a first distance and the first doped region is spaced apart from the source and drain regions a second distance.
Claim 8
Dependent Claim
15 words
The process of claim 6, wherein the first distance is greater than the second distance.
Claim 9
Dependent Claim
29 words
The process of claim 2, wherein the step of forming the first doped region further comprises ion implantation into the channel region prior to depositing the first semiconductor layer.
Claim 10
Dependent Claim
65 words
The process of claim 1, further comprising steps of: providing a masking layer overlying the surface, the masking layer having an opening therein exposing the channel region; and depositing a first semiconductor layer overlying the masking layer and the channel region, wherein the step of forming a first doped region further comprises ion implantation into the channel region prior to depositing the first semiconductor layer.
References Cited (Backward Citations)
JPS53112069A
Cited
US4371955A
Cited
US4599118A
Cited
US4680604A
Cited
US4697198A
Cited
US5021845A
Cited
US5082794A
Cited
US5175119A
Cited
US5399508A
Cited
US5374574A
Cited
US5374575A
Cited
US5372960A
Cited
US5427964A
Cited
US5482878A
Cited
US5434093A
Cited
US5429956A
Cited
US5472897A
Cited
US5484743A
Cited
US5538913A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-02-25 | 2000-08-26 | 2001-02-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-02-25 | 2004-08-26 | 2005-02-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-02-25 | 2008-08-26 | 2009-02-25 | $7700.00 | Window Closed / Lapsed |