Dual port memory, such as used in color lookup tables for video systems

Claim 2

On an integrated circuit, a circuit including a first memory cell having a left edge, a right edge, an upper edge, and a lower edge and having an upper part adjacent to said upper edge and a lower part adjacent to said lower edge, wherein the first memory cell comprises: a substrate of a first doping type; a first layer of regions including: a well of a second doping type located in said lower part of said memory cell; a first region and a second region of the second doping type, said first region extending to the left and upper edges, and said second region extending to the upper and right edges; a third region, a fourth region, and a fifth region of the first doping type, said third region in said lower part and extending from said left edge, said fourth region in said lower part and extending from said right edge, said fifth region in said lower part and extending from said lower edge; first, second, third, and fourth polysilicon regions; said first polysilicon region extending across said first region, said third region and said fifth region; said second polysilicon region extending across said second region and said fourth region; said third polysilicon region extending from said left edge to said right edge and extending across said fifth region; said fourth polysilicon region extending from said left edge to said right edge and extending across said first and second regions; and a first set of contacts including: a first contact connected to said first polysilicon region; a second contact connected to said second polysilicon region; a third contact connected to said first region; a fourth contact connected to said first region and located astride said left edge; a fifth contact connected to said first region and located astride said upper edge; a sixth contact connected to said second region; a seventh contact connected to said second region and located astride said right edge; an eighth contact connected to said second region and located astride said upper edge; a ninth contact connected to said third region; a tenth contact connected to said fourth region; an eleventh contact connected to said fourth region and located astride said right edge; a twelfth contact connected to said fifth region and located astride said lower edge; and a thirteenth contact connected to said fifth region; a second layer of regions including: a first metal region extending from said upper edge and connecting said fifth contact to a fourteenth contact; a second metal region extending from said upper edge and connecting said eighth contact to a fifteenth contact; a third metal region extending from said left edge to said right edge and located in said upper part of said memory cell; a fourth metal region extending from said left edge and connecting said fourth contact to a sixteenth contact; a fifth metal region connecting said second, third, and ninth contacts; a sixth metal region connecting said first, sixth, and tenth contacts; a seventh metal region extending from said right edge and connecting said seventh contact to a seventeenth contact; an eighth metal region extending from said left edge to said right edge and connecting said eleventh and thirteenth contacts; a ninth metal region extending from said left edge to said right edge and located in said lower part of said memory cell; a tenth metal region extending from said lower edge and connecting said twelfth contact to an eighteenth contact; and a third layer of regions, each region extending from said upper edge to said lower edge, including: an eleventh metal region connected to said sixteenth contact; a twelfth metal region connected to said fourteenth contact; a thirteenth metal region connected to said eighteenth contact; a fourteenth metal region connected to said fifteenth contact; and a fifteenth metal region connected to said seventeenth contact.

Claim 3

The circuit of claim 1, further comprising: a second memory cell, adjacent to and substantially a mirror image of the first memory cell about the upper edge of the first memory cell.

Claim 4

The circuit of claim 1, further comprising: a second memory cell substantially identical to the first memory cell, wherein the first and second memory cells are adjacent each other at the right edge of the first memory cell and at the left edge of the second memory cell.

Claim 5

The circuit of claim 3, further comprising: a third memory cell and a fourth memory cell adjacent each other, and adjacent to and substantially a mirror image of the first and second memory cells about the upper edges of the first and second memory cells.

Claim 6

A memory cell on an integrated circuit, the integrated circuit having a substrate of a first doping type and within the substrate a well of a second doping type the memory cell having first, second, third, and fourth edges, and the memory cell having an upper part and a lower part, said well located in said lower part, and comprising: A) a static memory device including: a first polysilicon member (202) extending across portions of said upper and lower parts, and having a first contact (251); a second polysilicon member (206) extending across portions of said upper and lower parts, and having a second contact (250) said upper part, including: a first region (212) of the second doping type and extending to the first and second edges; third (242), fourth (243), and fifth (244) contacts connected to the first region, the fourth and fifth contacts being astride the first and second edges, respectively; a portion of the first polysilicon member being in proximity with a first portion of the first region to form a first transistor (100) of a first channel type, the third and fourth contacts being first and second channel terminals of the first transistor, respectively; a second region (213) of the second doping type and extending to the second and third edges sixth (245), seventh (246), and eighth (247) contacts connected to the second region, the seventh and eighth contacts being astride the third and second edges, respectively, and a portion of the second polysilicon member being in proximity with a first portion of the second region to form a second transistor (102) of the first channel type, the sixth and seventh contacts being first and second channel terminals of the second transistor, respectively; said lower part including: a third region (203) of the first doping type and extending to the first edge; a ninth contact (234) connected to the third region; a portion of the first polysilicon member being in proximity with a portion of the third region to form a third transistor (101) of a second channel type, the ninth contact being a first channel terminal of the third transistor; a fourth region (205) of the first doping type and extending to the third edge; tenth (235) and eleventh (238) contacts connected to the fourth region, the eleventh contact being astride the third edge; and a portion of the second polysilicon member being in proximity with a portion of the fourth region to form a fourth transistor (103) of the second channel type, the tenth and eleventh contacts being first and second channel terminals of the fourth transistor, respectively; B) a read-write port (117), in said upper part, the read-write port including: a third polysilicon member (214) extending from the first edge to the third edge; a portion of the third polysilicon member being in proximity with a portion of the first region to form a fifth transistor (114) of the second channel type, the third and fifth contacts being first and second channel terminals of the fifth transistor, respectively; a portion of the third polysilicon member being in proximity with a portion of the second region to form a sixth transistor (112) of the second channel type, the sixth and eighth contacts being first and second channel terminals of the sixth transistor, respectively; and wherein the third polysilicon member may conduct a first word line signal (CP 13 WLZ) to access the memory device for reading or writing, and the fifth and eighth contacts may carry true and complement values (BIT and BITZ) of a bit read from or written to the memory device; and C) a high-speed read-only port (106) in said lower part, the high-speed read-only port including: a fifth region (200) of the first doping type and extending to the fourth edge; a twelfth contact (230) and at least one thirteenth contact (231, 232, 233) connected to the fifth region, the twelfth contact being astride the fourth edge; a portion of the first polysilicon member being in proximity with a first portion of the fifth region, to form a seventh transistor (107) of the first channel type, the at least one thirteenth contact being a first channel terminal of the seventh transistor; a fourth polysilicon member (201) extending from the first edge to the third edge; a portion of the fourth polysilicon member being in proximity with a second portion of the fifth region to form an eighth transistor (109) of the first channel type, the twelfth contact being a first channel terminal of the eighth transistor; and wherein the fourth polysilicon member conducts a second word line signal (V 13 WL) to access the memory device for high-speed reading, and the twelfth contact may carry a value (VOUTZ) of a bit read from the memory device.

Claim 7

A memory cell on an integrated circuit, the integrated circuit having a substrate of a first doping type and within the substrate a well of a second doping type the memory cell having first, second, third, and fourth edges, and the memory cell having an upper part and a lower part, said well located in said lower part, and comprising: A) a static memory device including: a first polysilicon member (202) extending across portions of said upper and lower parts, and having a first contact (251); a second polysilicon member (206) extending across portions of said upper and lower parts, and having a second contact (250) said upper part, including: a first region (212) of the second doping type and extending to the first and second edges; third (242), fourth (243), and fifth (244) contacts connected to the first region, the fourth and fifth contacts being astride the first and second edges, respectively; a portion of the first polysilicon member being in proximity with a first portion of the first region to form a first transistor (100) of a first channel type, the third and fourth contacts being first and second channel terminals of the first transistor, respectively; a second region (213) of the second doping type and extending to the second and third edges sixth (245), seventh (246), and eighth (247) contacts connected to the second region, the seventh and eighth contacts being astride the third and second edges, respectively, and a portion of the second polysilicon member being in proximity with a first portion of the second region to form a second transistor (102) of the first channel type, the sixth and seventh contacts being first and second channel terminals of the second transistor, respectively; said lower part including: a third region (203) of the first doping type and extending to the first edge; a ninth contact (234) connected to the third region; a portion of the first polysilicon member being in proximity with a portion of the third region to form a third transistor (101) of a second channel type, the ninth contact being a first channel terminal of the third transistor; a fourth region (205) of the first doping type and extending to the third edge; tenth (235) and eleventh (238) contacts connected to the fourth region, the eleventh contact being astride the third edge; and a portion of the second polysilicon member being in proximity with a portion of the fourth region to form a fourth transistor (103) of the second channel type, the tenth and eleventh contacts being first and second channel terminals of the fourth transistor, respectively; B) a read-write port (117), in said upper part, the read-write port including: a third polysilicon member (214) extending from the first edge to the third edge; a portion of the third polysilicon member being in proximity with a portion of the first region to form a fifth transistor (114) of the second channel type, the third and fifth contacts being first and second channel terminals of the fifth transistor, respectively; a portion of the third polysilicon member being in proximity with a portion of the second region to form a sixth transistor (112) of the second channel type, the sixth and eighth contacts being first and second channel terminals of the sixth transistor, respectively; and wherein the third polysilicon member may conduct a first word line signal (CP 13 WLZ) to access the memory device for reading or writing, and the fifth and eighth contacts may carry true and complement values (BIT and BITZ) of a bit read from or written to the memory device; and C) a high-speed read-only port (106) in said lower part, the high-speed read-only port including: a fifth region (200) of the first doping type and extending to the fourth edge; a twelfth contact (230) and at least one thirteenth contact (231, 232, 233) connected to the fifth region, the twelfth contact being astride the fourth edge; a portion of the first polysilicon member being in proximity with a first portion of the fifth region, to form a seventh transistor (107) of the first channel type, the at least one thirteenth contact being a first channel terminal of the seventh transistor; a fourth polysilicon member (201) extending from the first edge to the third edge; a portion of the fourth polysilicon member being in proximity with a second portion of the fifth region to form an eighth transistor (109) of the first channel type, the twelfth contact being a first channel terminal of the eighth transistor; and wherein the fourth polysilicon member conducts a second word line signal (V 13 WL) to access the memory device for high-speed reading, and the twelfth contact may carry a value (VOUTZ) of a bit read from the memory device.

Claim 8

The memory cell of claim 5, wherein said static memory device, said read-write port, and said high speed read only port are included in a first layer of regions.

Claim 9

The memory cell of claim 6, further comprising a second layer of regions, including: a sixth region extending from said second edge and connecting said fifth contact to a fourteenth contact; a seventh region extending from said second edge and connecting said eighth contact to a fifteenth contact; an eighth region extending from said first edge to said third edge and located in said upper part of said memory cell; a ninth region extending from said first edge and connecting said fourth contact to a sixteenth contact; a tenth region connecting said second, third, and ninth contacts; an eleventh region connecting said first, sixth, and tenth contacts; a twelfth region extending from said first edge and connecting said seventh contact to a seventeenth contact; a thirteenth region extending from said third edge to said first edge and connecting said eleventh and thirteenth contacts; a fourteenth region extending from said first edge to said third edge and located in said lower portion of said memory cell; and a fifteenth region extending from said fourth edge and connecting said twelfth contact to an eighteenth contact.

Claim 10

The memory cell of claim 7, further comprising a third layer of regions, each extending from said second edge to said fourth edge, including: a sixteenth region connected to said sixteenth contact; a seventeenth region connected to said fourteenth contact; an eighteenth region connected to said eighteenth contact; a nineteenth region connected to said fifteenth contact; and a twentieth region connected to said seventeenth contact.