Method and apparatus for accessing a color palette synchronously during refreshing of a monitor and asynchronously during updating of the palette

Claim 2

A color graphics system comprising: a memory; a first source of memory addresses; a second source of memory addresses; a source of clock pulses; a source of a first and a second control signal; means connected to said memory, said first source of memory addresses, said second source of memory addresses, said source of clock pulses, and said source of said first and said second control signals for selectively accessing said memory in a synchronous manner using addresses from said first source of memory addresses in synchronism with clock pulses from said source of clock pulses in response to said first control signal and in an asynchronous manner using addresses from said second source of memory addresses independent of said clock pulses in response to said second control signal.

Claim 3

A system according to claim 1 wherein said source of clock pulses comprises a video timing generator and said clock pulses from said source comprise pixel clock pulses having a pulse rate used for scanning pixels on a monitor in said system.

Claim 4

A system according to claim 1 wherein said memory comprises a random access memory, said first source of memory addresses comprises a video address bus and said second source of memory addresses comprises a central processing unit system address bus.

Claim 5

A system according to claim 1 wherein said memory accessing means comprises: means for registering said addresses from said first and second sources of memory addresses; and means for selectively transferring said addresses from said first source of memory addresses to said means for registering said addresses in synchronism with said clock pulses from said source of clock pulses in response to said first control signal and from said second source of memory addresses to said means for registering said addresses in an asynchronous manner in response to said second control signal.

Claim 6

A system according to claim 4 wherein said first source of memory addresses comprises a video address bus, said second source of memory addresses comprises a central processing unit (CPU) system address bus, and said transferring means comprises means for transferring addresses from said video address bus to said means for registering said addresses in response to said first control signal and from said CPU system address bus to said means for registering said addresses in response to said second control signal.

Claim 7

A system according to claim 5 wherein said transferring means comprises: a multiplexer having a first output coupled to said video address bus; a second input coupled to said system address bus; an output coupled to said means for registering said addresses; a control signal input coupled to a source of said first and said second control signals; and means responsive to said first and said second control signals for selectively coupling said first and said second inputs and said output.

Claim 8

A system according to claim 1 wherein said first source of memory addresses comprises: a video display memory; and means for transferring an address from said video display memory to a video address bus.

Claim 9

A system according to claim 7 wherein said means for transferring an address from said video display memory to a video address bus comprises: means located between said video display memory and said video address bus for registering said addresses from said video display memory; means for transferring a plurality of addresses in parallel from said video display memory to said address registering means; and means for transferring each of said addresses sequentially from said address registering means to said video address bus.

Claim 10

A system according to claim 1 wherein said memory accessing means comprises: means having an output for registering data; and means located in said data registering means for selectively transferring a data word from said memory to said output of said data registering means in synchronism with said clock pulses in response to said first control signal and from said memory to said output of said data registering means in an asynchronous manner independent of said clock pulses in response to said second control signal.

Claim 11

A system according to claim 9 comprising: means having a digital input, an analog output and an input for receiving said clock pulses for converting digital signals to analog signals; a video monitor having means for illuminating colored pixel triads on a screen; means for coupling said digital input to said output of said data registering means; and means for coupling said analog output to said colored pixel triad illuminating means.

Claim 12

A system according to claim 4 wherein said means for registering said addresses comprises: first and second means for gating signals and first and second means for latching signals, each of said gating and latching means comprising an input for receiving an input signal, an output for providing an output signal, an input for receiving clock pulses and an input for receiving said first and said second control signals; means for coupling said outputs of said first gating means and said first latching means to said inputs of said first latching means and said second gating means; means for coupling said outputs of said second gating means and said second latching means to said input of said second latching means; means for coupling all of said inputs for receiving said clock pulses in parallel to said source of clock pulses; means for coupling all of said inputs for receiving said first and said second control signals in parallel to said source of said control signals; and means located in said gating and latching means for selectively transferring an input signal applied to said input of said first gating means to said output of said second latching means in synchronism with said clock pulses in response to said first control signal and asynchronously independent of said clock pulses in response to said second control signal.

Claim 13

A system according to claim 9 wherein said data registering means comprises: first and second means for gating signals and first and second means for latching signals, each of said gating and latching means comprising an input for receiving an input signal, an output for providing an output signal, an input for receiving clock pulses and an input for receiving said first and said second control signals; means for coupling said outputs of said first gating means and said first latching means to said inputs of said first latching means and said second gating means; means for coupling said outputs of said second gating means and said second latching means to said input of said second latching means; means for coupling all of said inputs for receiving said clock pulses in parallel to said source of clock pulses; means for coupling all of said inputs for receiving said first and said second control signals in parallel to said source of said control signals; and means located in said gating and latching means for selectively transferring an input signal applied to said input of said first gating means to said output of said second latching means in synchronism with said clock pulses in response to said first control signal and asynchronously independent of said clock pulses in response to said second control signal.

Claim 14

A color graphics system comprising: a memory; a first source of memory addresses; a second source of memory addresses; a source of clock pulses; a color monitor; and means for selectively accessing said memory to refresh said monitor using words from said memory which are accessed using addresses from said first source of addresses in synchronism with said clock pulses in response to a first control signal and to write into and read from said memory using addresses from said second source of addresses asynchronously independent of said clock pulses in response to a second control signal.

Claim 15

A color graphics system comprising: a memory; a first source of memory addresses; a second source of memory addresses; a source of clock pulses; a color monitor; and means for selectively accessing said memory to refresh said monitor using words from said memory which are accessed using addresses from said first source of addresses in synchronism with said clock pulses in response to a first control signal and to write into and read from said memory using addresses from said second source of addresses asynchronously independent of said clock pulses in response to a second control signal.

Claim 16

A system according to claim 13 wherein said accessing means comprises means for registering addresses and data coupled to said memory and said registering means comprises: first and second means for gating signals and first and second means for latching signals, each of said gating and latching means comprising an input for receiving an input signal, an output for providing an output signal, an input for receiving clock pulses and an input for receiving said first and said second control signals; means for coupling said outputs of said first gating means and said first latching means to said inputs of said first latching means and said second gating means; means for coupling said outputs of said second gating means and said second latching means to said input of said second latching means; means for coupling all of said inputs for receiving said clock pulses in parallel to said source of clock pulses; means for coupling all of said inputs for receiving said first and said second control signals in parallel to said source of said control signals; and means located in said gating and latching means for selectively transferring an input signal applied to said input of said first gating means to said output of said second latching means in synchronism with said clock pulses in response to said first control signal and asynchronously independent of said clock pulses in response to said second control signal.

Claim 17

In a color graphics system having: a memory; a first source of memory addresses; a second source of memory addresses; a source of clock pulses; and a source of a first and a second control signal; a method of accessing said memory comprising the steps of: accessing said memory in a synchronous manner using addresses from said first source of memory addresses in synchronism with clock pulses from said source of clock pulses in response to said first control signal; and accessing said memory in an asynchronous manner using addresses from said second source of memory addresses independent of said clock pulses in response to said second control signal.

Claim 18

In a color graphics system having: a memory; a first source of memory addresses; a second source of memory addresses; a source of clock pulses; and a source of a first and a second control signal; a method of accessing said memory comprising the steps of: accessing said memory in a synchronous manner using addresses from said first source of memory addresses in synchronism with clock pulses from said source of clock pulses in response to said first control signal; and accessing said memory in an asynchronous manner using addresses from said second source of memory addresses independent of said clock pulses in response to said second control signal.

Claim 19

A method according to claim 15 wherein said step of using addresses in synchronism with clock pulses from said source of clock pulses comprises the step of using addresses in synchronism with pixel clock pulses from a video timing generator, said pixel clock pulses having a pulse rate used for scanning pixels on a monitor in said system.

Claim 20

A method according to claim 15 wherein each of said steps of accessing said memory comprises the step of accessing a random access memory, said step of using addresses from said first source of memory addresses comprises the step of using addresses from a video address bus and said step of using addresses from said second source of memory addresses comprises the step of using addresses from a central processing unit system address bus.

Claim 21

A method according to claim 15 wherein said accessing steps comprise the steps of: transferring said addresses from said first source of memory addresses to an address registering means in synchronism with said clock pulses from said source of clock pulses in response to said first control signal; and transferring said addresses from said second source of memory addresses to said address registering means in an asynchronous manner in response to said second control signal.

Claim 22

A method according to claim 18 wherein said first source of memory addresses comprises a video address bus, said second source of memory addresses comprises a central processing unit (CPU) system address bus, and said transferring steps comprise the steps of: transferring addresses from said video address bus to said address registering means in synchronism with said clock pulses in response to said first control signal; and transferring addresses from said CPU system address bus to said address registering means independent of said clock pulses in response to said second control signal.

Claim 23

A method according to claim 19 wherein said transferring steps comprise the steps of: providing a multiplexer having a first input coupled to said video address bus; a second input coupled to said system address bus; an output coupled to said address registering means; a control signal input coupled to a source of said first and said second control signals; and selectively coupling said first and said second inputs and said output in response to said first and said second control signals, respectively.

Claim 24

A method according to claim 20 wherein said first source of memory addresses comprises: a video display memory; and said transferring steps comprise the step of: transferring an address from said video display memory to said video address bus.

Claim 25

A method according to claim 21 wherein said latter address transferring step comprises the steps of: registering said addresses from said video display memory in a means for registering addresses located between said video display memory and said video address bus; transferring a plurality of addresses in parallel from said video display memory to said latter address registering means; and transferring each of said addresses sequentially from said latter address registering means to said video address bus.

Claim 26

A method according to claim 15 wherein said memory accessing steps comprises the steps of: transferring a data word from said memory to a data registering means in synchronism with said clock pulses in response to said first control signal; and transferring a data word from said memory to said data registering means in an asynchronous manner independent of said clock pulses in response to said second control signal.

Claim 27

A method according to claim 23 comprising the steps of: providing a means having a digital input, an analog output and an input for receiving said clock pulses for converting digital signals to analog signals; and providing a video monitor having means for illuminating colored pixel triads on a screen; and wherein said transferring steps comprise the steps of: coupling said digital input to said output of said data registering means; and coupling said analog output to said colored pixel triad illuminating means.

Claim 28

A method according to claim 15 wherein said memory accessing steps comprise the steps of: providing a first and second means for gating signals and first and second means for latching signals, each of said gating and latching means comprising an input for receiving an input signal, an output for providing an output signal, an input for receiving clock pulses and an input for receiving said first and said second control signals; providing means for coupling said outputs of said first gating means and said first latching means to said inputs of said first latching means and said second gating means; providing means for coupling said outputs of said second gating means and said second latching means to said input of said second latching means; providing means for coupling all of said inputs for receiving said clock pulses in parallel to said source of clock pulses; providing means for coupling all of said inputs for receiving said first and said second control signals in parallel to said source of said control signals; and providing means located in said gating and latching means for selectively transferring an input signal applied to said input of said first gating means to said output of said second latching means in synchronism with said clock pulses in response to said first control signal and asynchronously independent of said clock pulses in response to said second control signal.