Multifunction network

Claim 2

A single chip integrated circuit multifunction network and connector terminal means for connecting circuits in the network through a mating connector to a plurality of bidirectional buses and to means producing first and second function signals and mode selection signals, said multifunction network comprising: a plurality of page registers for storing page values; a plurality of index registers for storing index values; decoder means enabled by said mode selection signals and responsive to signals on a first of said buses for selectively producing one of a plurality of signals designating a page or index register to be loaded; first means connected to a second of said buses, said first means being responsive to the signal produced by said decoder means, and to said first function signal for loading the designated page or index register with the value represented by signals on said second bus; a storage address register; means connected to said storage address register for applying page and index values in said storage address register to a third of said buses; and, second means responsive to signals on a further of said buses for gating a page and an index value from said page and index registers, respectively, to said storage address register.

Claim 3

A multifunction network as claimed in claim 1 wherein said second means includes: further gating means for receiving signals from both a fourth and a fifth of said buses, said further gating means being responsive to said second function signal for selecting the signals on one of said fourth and fifth buses as the signals for gating a page and an index value to said storage address register.

Claim 4

A multifunction network as claimed in claim 1 wherein a signal from said first bus is applied as a load enabling signal to said storage address register.

Claim 5

A multifunction network as claimed in claim 1 wherein said first means includes means responsive to selected ones of said plurality of signals generated by said decoder means for loading a second designated page or index register with signals from another of said buses simultaneously with the loading of said designated page or index register.

Claim 6

A multifunction network as claimed in claim 1 wherein said decoder means produces further signals designated one or more page and index registers to be read out, said multifunction network further comprising means responsive to said further signals for gating the values in the designated page or index registers to said second bus and another of said buses.

Claim 7

A single chip integrated circuit multifunction network and connector terminal means for connecting circuits in the network through a mating connector to first, second, third, fourth, fifth and sixth bidirectional buses, to sources of first and second function control signals, to a source of chip enable signals and to first and second mode selection signals, said multifunction network comprising: first, second, third, fourth, fifth and sixth receiver means, there being a receiver means associated with each of said buses for receiving signals therefrom; first, second, third, fourth, fifth and sixth driver means, there being a driver means associated with each of said buses for applying signals thereto; said receiver means and said driver means being enabled in response to said chip enable signals; mode decode means responsive to said first and second mode selection signals for producing mode signals each indicating a selected mode in which the multifunction network is to operate; function means responsive to said function control signals for producing first and second function signals indicating a function to be performed within a selected mode; first circuit means responsive to signals from said first, second, third, fourth and sixth receiver means, a first of said mode signals from said mode decode means, and said function signals for applying to said fifth driver means signals representing a value on said first, second, third or fourth bus; second circuit means connected to said fifth receiver means and responsive to said first of said mode signals and said first and second function signals for applying signals representing a value on said fifth bus to one of said first, second, third or fourth driver means; a first Exclusive OR circuit connected to said first, second, third, fourth and sixth receiver means for generating the Exclusive OR of corresponding bit positions on said first, second, third, fourth and sixth buses; a second Exclusive OR circuit connected to said fifth receiver means and said first Exclusive OR circuit for generating the Exclusive OR of corresponding bit positions of all said buses; and, further means responsive to a second of said mode signals and said first and second function signals for applying the outputs from said second Exclusive OR circuit to all said driver means when said first and second function signals have a first combination of states, for applying the outputs from said first Exclusive OR circuit to said fifth driver means when said first and second function signals have a second combination of states, and connecting said fifth receiver means to said first, second, third, fourth and sixth driver means when said first and second function signals have a third combination of states.

Claim 8

A single chip integrated circuit multifunction network and connector terminal means for connecting circuits in the network through a mating connector to first, second, third, fourth, fifth and sixth bidirectional buses, to sources of first and second function control signals, to a source of chip enable signals and to first and second mode selection signals, said multifunction network comprising: first, second, third, fourth, fifth and sixth receiver means, there being a receiver means associated with each of said buses for receiving signals therefrom; first, second, third, fourth, fifth and sixth driver means, there being a driver means associated with each of said buses for applying signals thereto; said receiver means and said driver means being enabled in response to said chip enable signals; mode decode means responsive to said first and second mode selection signals for producing mode signals each indicating a selected mode in which the multifunction network is to operate; function means responsive to said function control signals for producing first and second function signals indicating a function to be performed within a selected mode; first circuit means responsive to signals from said first, second, third, fourth and sixth receiver means, a first of said mode signals from said mode decode means, and said function signals for applying to said fifth driver means signals representing a value on said first, second, third or fourth bus; second circuit means connected to said fifth receiver means and responsive to said first of said mode signals and said first and second function signals for applying signals representing a value on said fifth bus to one of said first, second, third or fourth driver means; a first Exclusive OR circuit connected to said first, second, third, fourth and sixth receiver means for generating the Exclusive OR of corresponding bit positions on said first, second, third, fourth and sixth buses; a second Exclusive OR circuit connected to said fifth receiver means and said first Exclusive OR circuit for generating the Exclusive OR of corresponding bit positions of all said buses; and, further means responsive to a second of said mode signals and said first and second function signals for applying the outputs from said second Exclusive OR circuit to all said driver means when said first and second function signals have a first combination of states, for applying the outputs from said first Exclusive OR circuit to said fifth driver means when said first and second function signals have a second combination of states, and connecting said fifth receiver means to said first, second, third, fourth and sixth driver means when said first and second function signals have a third combination of states.

Claim 9

A multifunction network as claimed in claim 6 wherein said further means includes a latch means connected to said second Exclusive OR circuit; an error location matrix having inputs connected to said latch means and outputs connected to said sixth driver means; and, gating means connecting said latch means to all said driver means.

Claim 10

A multifunction network as claimed in claim 6 and further comprising: first, second, third and fourth latch means; and, loading means connected to said first and second function signals for loading a value from the first bus into one of said latch means as determined by said first and second function signals.

Claim 11

A multifunction network as claimed in claim 9 including means connecting said sixth receiver means to said loading means whereby a signal on the sixth bus may time the loading of said one latch means.

Claim 12

A multifunction network as claimed in claim 9 and further comprising: gating means connected between said first, second, third and fourth latch means and said first driver means, and responsive to said first and second function signals and a further signal on said sixth bus for transferring a value in one of said latch means to said first bus.

Claim 13

A multifunction network as claimed in claim 8 wherein said loading means includes gating means connected to said sixth receiver means and connected between said second, third, fourth and fifth receivers and said first, second, third and fifth latch means, respectively, and responsive to signals on said sixth bus, said sixth bus signals designating one or more of said latch means which is to be loaded from one or more of said buses.

Claim 14

A multifunction network as claimed in claim 11 and further including gating means connected to said sixth receiver means and responsive to signals therefrom for transferring values in selected ones of said latch means to selected ones of said driver means.