Interrupt circuitry for microprocessor chip

Claim 2

In a microprocessor, circuitry for effecting execution of an interrupt operation of said microprocessor in response to a interrupt request signal comprising: data bus means for transferring digital information, said data bus means being capable of being coupled to a memory means having an interrupt routine program stored therein; register stroage means coupled to said data bus means for temporarily storing digital information in accordance with execution of various instructions by said microprocessor, including an instruction for setting an interrupt mask bit; an interrupt request conductor for conducting said interrupt request signal; instruction register means coupled to said data bus means for temporarily storing each instruction as it is received from said data bus means; instruction decode means coupled to said instruction register means for controlling said register storage means and said data bus means to effect execution of the instruction stored in said instruction register means; interrupt means coupled to said interrupt request conductor and said instruction register means for inhibiting said temporary storing of the next instruction to be executed in response to said interrupt request signal; means responsive to said interrupt means for internally generating a fixed code instruction within said instruction register means; and circuit means in said instruction decode means for effecting transferring digital information in said register stroage means to said memory means and causing said microprocessor to branch to said interrupt routine program.

Claim 3

Circuitry as recited in claim 1 further including second circuit means coupled to said instruction decode means for generating a fixed address vector which causes said microprocessor to address a fixed location in said memory means corresponding to said fixed address vector and which causes said microprocessor to read stored information from said fixed location, said stroed information being the address of the first instruction of said interrupt routine program.

Claim 4

Circuitry as recited in claim 2 wherein said microprocessor further includes address bus means coupled to said register storage means and capable of being coupled to said memory means for addressing said memory means, wherein said fixed address vector is transferred to said memory means via said address bus means in order to address said fixed location.

Claim 5

In a microprocessor integrated circuit chip, interrupt circuitry for controlling execution of a interrupt operation of said microprocessor in response to an interrupt request signal, said circuitry comprising: an interrupt request input; a first clock conductor; a second clock conductor; a first control conductor; a storage means for storing a mask bit; a first inverter having an input and an output, said input being coupled to said interrupt request input; a first NOR gate having first and second inputs and an output, said first input being coupled to said output of said first inverter; a first MOSFET having a gate, a drain, and a source, said gate being coupled to said first clock conductor and said drain being coupled to said second input of said first NOR gate; a first NAND gate having first and second inputs and an output, said first input of said first NAND gate being coupled to said output of said first NOR gate, said second input of said first NAND gate being coupled to said first control conductor; a second MOSFET having a gate, a drain, and a source, said gate of said second MOSFET being connected to said second clock conductor and said drain of said second MOSFET being coupled to said output of said first NAND gate; a frist AND gate having first and second input and having an output; a second inverter having an input and an output, said input of said second inverter being connected to said storage means, said first input of said first AND gate being connected to said output of said second inverter, and said second input of said first AND gate being connected to said source of said second MOSFET; a third MOSFET having a gate, a source, and a drain, said gate of said third MOSFET being connected to said first clock conductor, said drain of said third MOSFET being connected to said second input of said first AND gate; a sceond NOR gate having first and second inputs and an output, said first input of said second NOR gate being coupled to said output of said first AND gate, said second input of said second NOR gate being connected to said source of said third MOSFET and to said source of said first MOSFET; a third NOR gate having first and second inputs and an output, said output of said third NOR gate being coupled to said source of said third MOSFET, said first input of said third NOR gate being coupled to said output of said second NOR gate; a fourth MOSFET having a gate, a source, and a drain; a fifth MOSFET having a gate, a source, and a drain; said drain of said fourth MOSFET being connected to said first input of said third NOR gate, said gate of said fourth MOSFET being coupled to said first clock conductor, said second input of said third NOR gate being connected to said source of said fourth MOSFET and to said drain of said fifth MOSFET, said gate of said fifth MOSFET being connected to said second clock conductor, said source of said fifth MOSFET being coupled to said first control conductor; a sixth MOSFET having gate, a drain, and a source, said drain of said sixth MOSFET being connected to said output of said third NOR gate, said gate of said sixth MOSFET being connected to said first clock conductor.

Claim 6

In a microprocessor integrated circuit chip, interrupt circuitry for controlling execution of a interrupt operation of said microprocessor in response to an interrupt request signal, said circuitry comprising: an interrupt request input; a first clock conductor; a second clock conductor; a first control conductor; a storage means for storing a mask bit; a first inverter having an input and an output, said input being coupled to said interrupt request input; a first NOR gate having first and second inputs and an output, said first input being coupled to said output of said first inverter; a first MOSFET having a gate, a drain, and a source, said gate being coupled to said first clock conductor and said drain being coupled to said second input of said first NOR gate; a first NAND gate having first and second inputs and an output, said first input of said first NAND gate being coupled to said output of said first NOR gate, said second input of said first NAND gate being coupled to said first control conductor; a second MOSFET having a gate, a drain, and a source, said gate of said second MOSFET being connected to said second clock conductor and said drain of said second MOSFET being coupled to said output of said first NAND gate; a frist AND gate having first and second input and having an output; a second inverter having an input and an output, said input of said second inverter being connected to said storage means, said first input of said first AND gate being connected to said output of said second inverter, and said second input of said first AND gate being connected to said source of said second MOSFET; a third MOSFET having a gate, a source, and a drain, said gate of said third MOSFET being connected to said first clock conductor, said drain of said third MOSFET being connected to said second input of said first AND gate; a sceond NOR gate having first and second inputs and an output, said first input of said second NOR gate being coupled to said output of said first AND gate, said second input of said second NOR gate being connected to said source of said third MOSFET and to said source of said first MOSFET; a third NOR gate having first and second inputs and an output, said output of said third NOR gate being coupled to said source of said third MOSFET, said first input of said third NOR gate being coupled to said output of said second NOR gate; a fourth MOSFET having a gate, a source, and a drain; a fifth MOSFET having a gate, a source, and a drain; said drain of said fourth MOSFET being connected to said first input of said third NOR gate, said gate of said fourth MOSFET being coupled to said first clock conductor, said second input of said third NOR gate being connected to said source of said fourth MOSFET and to said drain of said fifth MOSFET, said gate of said fifth MOSFET being connected to said second clock conductor, said source of said fifth MOSFET being coupled to said first control conductor; a sixth MOSFET having gate, a drain, and a source, said drain of said sixth MOSFET being connected to said output of said third NOR gate, said gate of said sixth MOSFET being connected to said first clock conductor.

Claim 7

The interrupt circuit as recited in claim 4 further including: instruction register means for temporarily storing an instruction received by said microprocessor; circuit means coupled between said instruction register and said source of said sixth MOSFET for inhibiting loading of any other instruction and forcing an internally generated instruction into said instruction register in response to said interrupt request signal, conditionally upon whether said storage means contains said mask bit.