Extended addressing for programmed data processor having improved register loading means

Claim 2

A digital data processor for operation with an addressable memory and having plural registers including an accumulator register, an adder, a working register for transferring information with said memory, a noun register for applying an address signal to said memory, a pRogram counter, and a verb register for receiving instruction operation codes from said working register, each of said registers having plural stages so ordered that each stage in a register is associated with a different digit position, said processor further comprising a transfer bus interconnecting said registers and wherein; A. said transfer bus includes plural signal paths so ordered that each path is associated with one said digit position, and B. said working register includes: 1. first gate means for transferring information stored in a first group of stages therein associated with a first set of digit positions to the associated paths of said bus in response to a first working register output control signal, 2. second gate means for transferring information stored in a second group of stages therein associated with a second set of digit positions to the associated paths of said bus in response to a second working register output control signal, and 3. third gate means for transferring information stored in a third group of stages therein, said third group of stages selected from a subgroup of said first group of stages, to paths of said bus associated with said second set of digit positions in response to a third working register output control signal, and wherein said processor further comprises C. a sector register including fourth gate means for receiving information from bus paths associated with said second set of digit positions in response to a first sector register input control signal, and D. timing and control means operable to simultaneously produce said second working register and said first sector register control signals so as to transfer information from said second group of stages of said working register to said sector register, and further alternatively operable to simultaneously produce said third working register and said first sector register control signals so as to transfer information in said third group of stages of said working register to said sector register.

Claim 3

second gate means for transferring information stored in a second group of stages therein associated with a second set of digit positions to the associated paths of said bus in response to a second working register output control signal, and

Claim 4

second gate means for transferring information stored in a second group of stages therein associated with a second set of digit positions to the associated paths of said bus in response to a second working register output control signal, and

Claim 5

A processor as defined in claim 1 wherein: A. said transfer bus includes signal paths associated with a third set of digit positions in addition to paths associated with said first and second sets of digit positions, B. said working register includes:

Claim 6

a bistable control element connected to inhibit said first control signal when said second control signal is produced, and

Claim 7

a bistable control element connected to inhibit said first control signal when said second control signal is produced, and

Claim 8

a control element connected with said gate means for selectively inhibiting the storage of sector address bits from said program counter and from said sector register independent of said storage of word address bits in said noun register, for said loading of said selected sector address bits.

Claim 9

a control element connected with said gate means for selectively inhibiting the storage of sector address bits from said program counter and from said sector register independent of said storage of word address bits in said noun register, for said loading of said selected sector address bits.

Claim 10

second means for transferring the sector address bits from said program counter to said sector register, and

Claim 11

second means for transferring the sector address bits from said program counter to said sector register, and

Claim 12

means for loading said page and sector address bits from said counter into said noun register when said FSZ bit of said instruction word is in a first state, and

Claim 13

means for loading said page and sector address bits from said counter into said noun register when said FSZ bit of said instruction word is in a first state, and

Claim 14

means for transferring to said bus information stored in stages therein associated with said second and third sets of digit positions in response to a second program counter output control signal, and wherein: B. said timing and control means includes logic means for producing each of said firsT and second program counter output signals independent of each other and further includes a bistable device connected with said logic means for selectively inhibiting production of said second program counter output control signal.

Claim 15

means for transferring to said bus information stored in stages therein associated with said second and third sets of digit positions in response to a second program counter output control signal, and wherein: B. said timing and control means includes logic means for producing each of said firsT and second program counter output signals independent of each other and further includes a bistable device connected with said logic means for selectively inhibiting production of said second program counter output control signal.

Claim 16

means for transferring information stored therein in stages associated with said second and third sets of digit positions to associated paths of said bus in response to sector register output control signals, and wherein: D. said program counter is connected to receive information from said bus paths associated with said first, second and third sets of digit positions for storage in stages associated with said first, second and third digit positions in response to program counter input control signals.

Claim 17

means for transferring information stored therein in stages associated with said second and third sets of digit positions to associated paths of said bus in response to sector register output control signals, and wherein: D. said program counter is connected to receive information from said bus paths associated with said first, second and third sets of digit positions for storage in stages associated with said first, second and third digit positions in response to program counter input control signals.

Claim 18

A processor as defined in claim 2 wherein: A. said program counter includes:

Claim 19

means for loading said page and sector address bits from said sector register into said noun register when said FSZ bit of said instruction word is in a second state.

Claim 20

means for loading said page and sector address bits from said sector register into said noun register when said FSZ bit of said instruction word is in a second state.

Claim 21

third means for transferring to said program counter said sector address bits loaded in said noun register from said sector register by said first means for transferring; B. means for detecting the termination of said branch instruction; and C. means for restoring to said program counter said sector address bits loaded in said sector register from said program counter by said second means for transferring when said means detecting detects the termination of said branch instruction.

Claim 22

third means for transferring to said program counter said sector address bits loaded in said noun register from said sector register by said first means for transferring; B. means for detecting the termination of said branch instruction; and C. means for restoring to said program counter said sector address bits loaded in said sector register from said program counter by said second means for transferring when said means detecting detects the termination of said branch instruction.

Claim 23

further gate means for storing selected sector address bits in said noun register in the absence of sector address bits from any one of said program counter and said sector register.

Claim 24

further gate means for storing selected sector address bits in said noun register in the absence of sector address bits from any one of said program counter and said sector register.

Claim 25

third gate means for transferring information stored in a third group of stages therein, said third group of stages selected from a subgroup of said first group of stages, to paths of said bus associated with said second set of digit positions in response to a third working register output control signal, and wherein said processor further comprises C. a sector register including fourth gate means for receiving information from bus paths associated with said second set of digit positions in response to a first sector register input control signal, and D. timing and control means operable to simultaneously produce said second working register and said first sector register control signals so as to transfer information from said second group of stages of said working register to said sector register, and further alternatively operable to simultaneously produce said third working register and said first sector register control signals so as to transfer information in said third group of stages of said working register to said sector register.

Claim 26

third gate means for transferring information stored in a third group of stages therein, said third group of stages selected from a subgroup of said first group of stages, to paths of said bus associated with said second set of digit positions in response to a third working register output control signal, and wherein said processor further comprises C. a sector register including fourth gate means for receiving information from bus paths associated with said second set of digit positions in response to a first sector register input control signal, and D. timing and control means operable to simultaneously produce said second working register and said first sector register control signals so as to transfer information from said second group of stages of said working register to said sector register, and further alternatively operable to simultaneously produce said third working register and said first sector register control signals so as to transfer information in said third group of stages of said working register to said sector register.

Claim 27

In a digital data processor having a plurality of multistage registers, wherein each of said stages comprises a bistable storage device having an input and an output for respectively receiving and sending signals, the combination comprising: A. first and second switch means: B. first gate means coupled for control by said first switch means and connected to transfer said signals to said bistable storage device input when enabled by said first switch means; C. second gate means coupled for control by said second switch means and connected in a first path to transfer a signal stored in said device to said first gate means when said second gate means is enabled by said second switch means; D. third gate means having an input and an output coupled in the connection of said first path between said second and first gate means, so that said second gate means and said third gate means input forms a first junction and so that the coupling of said third gate means output and said first gate means forms a second junction; E. third switch means coupled in a first mode to enable said third gate means for transfer of said signal to said first gate means and coupled in a second mode to transfer a preselected signal to said first gate means for storage in said device.

Claim 28

In a digital data processor having a plurality of multistage registers, wherein each of said stages comprises a bistable storage device having an input and an output for respectively receiving and sending signals, the combination comprising: A. first and second switch means: B. first gate means coupled for control by said first switch means and connected to transfer said signals to said bistable storage device input when enabled by said first switch means; C. second gate means coupled for control by said second switch means and connected in a first path to transfer a signal stored in said device to said first gate means when said second gate means is enabled by said second switch means; D. third gate means having an input and an output coupled in the connection of said first path between said second and first gate means, so that said second gate means and said third gate means input forms a first junction and so that the coupling of said third gate means output and said first gate means forms a second junction; E. third switch means coupled in a first mode to enable said third gate means for transfer of said signal to said first gate means and coupled in a second mode to transfer a preselected signal to said first gate means for storage in said device.

Claim 29

The combination as defined in claim 4 further comprising a transfer bus coupled at one end to said second junction and at the other end to a corresponding second junction of a corresponding device in another of said plurality of registers.

Claim 30

The combination as defined in claim 5 further comprising an indicator means coupled to said first path for indicating a signal representing said preselected signal when said first and second switch means are coupled to enable said first and second gate means, respectively.

Claim 31

The combination as defined in claim 6 wherein said indicator means is coupled to said second junction and wherein said indicator means indicates a signal similar to said preselected signal when said third switch means is in either of said first and second modes.

Claim 32

The combination as defined in claim 4 wherein said third switch means includes: A. means for enabling said signal stored in said device to be received by said first gate means; B. means for disabling said signal stored in said device from being received by said first gate means; and C. means for transferring said preselected signal to said first gate means for storage in said device when said means for disabling disables said signal stored in said device from being received by said first gate means.

Claim 33

In a digital data processor for operation with an addressable memory and having plural registers including an accumulator register, an adder, a working register for transferring information with said memory, a noun register for applying an address signal to said memory, a program counter, a verb register for receiving instruction operation codes from said working register, and a sector register arranged for transfer of information with said other plural registers, each of said registers having plural stages so ordered that each stage in a register is associated with a different digit position, said processor further having a transfer bus interconnecting said registers and wherein said address signal includes first instructions having word, sector and page addresses, each page including a plurality of sectors and each sector including a plurality of words, the method steps comprising: A. entering a fetch cycle; B. deciding whether to address said memory with the sector address stored in said sector register or with the sector address identified by an immediately preceding instruction; C. resetting the sector and page locations in sAid noun register to address a predetermined location in said memory and transferring the word address in said program counter into the word location of said noun register if said step of deciding determines that the sector address of said sector register is to be used to address said memory; D. placing the word, sector and page addresses in said program counter into said noun register if said step of deciding determines that the sector address of said immediately preceding instruction is to be used to address said memory; E. advancing said program counter by one memory position; F. resetting said working register; G. reading information including a second instruction having an operation code and a word address stored in the position in said memory currently addressed by said noun register into said working register; H. transferring the operation code in said working register into said verb register; I. determining from said operation code whether to address said memory with the sector address stored in said sector register or with the sector address identified by an immediately preceding instruction; J. transferring the sector and the page addresses contained in said sector register into the sector and page locations of said noun register and transferring the word address contained in said working register into the word location of said noun register if said step of determining indicates that the sector address of said sector register is to be used to address said memory; K. transferring the sector and page addresses contained in said program counter to the sector and page location in said noun register and transferring the word address contained in said working register to the word location of said noun register if said step of determining indicates that the sector address of an immediately preceding instruction is to be used to address said memory; and L. exiting said fetch cycle.

Claim 34

In a digital data processor for operation with an addressable memory and having plural registers including an accumulator register, an adder, a working register for transferring information with said memory, a noun register for applying an address signal to said memory, a program counter, a verb register for receiving instruction operation codes from said working register, and a sector register arranged for transfer of information with said other plural registers, each of said registers having plural stages so ordered that each stage in a register is associated with a different digit position, said processor further having a transfer bus interconnecting said registers and wherein said address signal includes first instructions having word, sector and page addresses, each page including a plurality of sectors and each sector including a plurality of words, the method steps comprising: A. entering a fetch cycle; B. deciding whether to address said memory with the sector address stored in said sector register or with the sector address identified by an immediately preceding instruction; C. resetting the sector and page locations in sAid noun register to address a predetermined location in said memory and transferring the word address in said program counter into the word location of said noun register if said step of deciding determines that the sector address of said sector register is to be used to address said memory; D. placing the word, sector and page addresses in said program counter into said noun register if said step of deciding determines that the sector address of said immediately preceding instruction is to be used to address said memory; E. advancing said program counter by one memory position; F. resetting said working register; G. reading information including a second instruction having an operation code and a word address stored in the position in said memory currently addressed by said noun register into said working register; H. transferring the operation code in said working register into said verb register; I. determining from said operation code whether to address said memory with the sector address stored in said sector register or with the sector address identified by an immediately preceding instruction; J. transferring the sector and the page addresses contained in said sector register into the sector and page locations of said noun register and transferring the word address contained in said working register into the word location of said noun register if said step of determining indicates that the sector address of said sector register is to be used to address said memory; K. transferring the sector and page addresses contained in said program counter to the sector and page location in said noun register and transferring the word address contained in said working register to the word location of said noun register if said step of determining indicates that the sector address of an immediately preceding instruction is to be used to address said memory; and L. exiting said fetch cycle.

Claim 35

In a digital data processor as defined in claim 9, the additional method steps comprising: A. entering an execution cycle; B. determining whether to address said memory with the sector address stored in said sector register or with the sector address identified by an immediately preceding instruction; C. transferring the sector and page addresses contained in said program counter into the sector and page locations of said sector register if said step of determining indicates that the sector address of said sector register is to be used to address said memory; D. resetting mode indicator means to indicate that the sector address identified by an immediately preceding instruction is to be addressed in said memory if said step of determining indicates that the sector address of an immediately preceding instruction is to be used to address said memory; E. resetting said working register; F. transferring the word and sector addresses contained in said program counter into the word and sector locations of said working register; G. writing the word and sector addresses contained in said working register into the position in said memory currently addressed by said noun register; H. resetting said program counter; I. transferring the word, sector and page addresses contained in said noun register into the word, sector and page locations of said program counter; J. advancing said program counter by one memory position; and K. exiting said execution cycle.

Claim 36

In a digital data processor as defined in claim 9, the additional method steps comprising: A. entering an execution cycle; B. determining whether to address said memory with the sector address stored in said sector register or with the sector address identified by an immediately preceding instruction; C. transferring the sector and page addresses contained in said program counter into the sector and page locations of said sector register if said step of determining indicates that the sectoR address of said sector register is to be used to address said memory; D. resetting said program counter; E. transferring the word, sector and page addresses contained in said noun register into the word, sector and page locations of said program counter; F. exiting said execution cycle.

Claim 37

A digital data processor for operation with an addressable memory and having a plurality of registers including a working register having m storage locations for transferring information with said memory, a noun register having n storage locations for applying an address word to said memory, a program counter having n storage locations, a verb register for receiving instruction words from said working register, and a sector register having k storage locations, said memory including a plurality of storage locations, each location in said memory including m bits of information, wherein k is less than m, and m is less than n, each stage of said above enumerated registers having a plural stages so ordered that each stage in a register is associated with a different digit position, said processor further comprising a transfer bus interconnecting said above enumerated registers, wherein said transfer bus includes plural signal paths so ordered that each path is associated with one said digit position, and further comprising; A. a plurality of memory address words each having n bits including bits designating a page address, a sector address within a page, and a word address within a sector; B. an instruction word having m bits including bits designated a word, an operation code and an FSZ bit, said FSZ bit designating the register source of a sector and page address; C. means for loading said program counter with one of said plurality of memory address words; D. means for loading said sector register with the page and sector bits of one of said plurality of memory address words; E. means for loading one of said plurality of memory address words into said noun register, including:

Claim 38

A digital data processor for operation with an addressable memory and having a plurality of registers including a working register having m storage locations for transferring information with said memory, a noun register having n storage locations for applying an address word to said memory, a program counter having n storage locations, a verb register for receiving instruction words from said working register, and a sector register having k storage locations, said memory including a plurality of storage locations, each location in said memory including m bits of information, wherein k is less than m, and m is less than n, each stage of said above enumerated registers having a plural stages so ordered that each stage in a register is associated with a different digit position, said processor further comprising a transfer bus interconnecting said above enumerated registers, wherein said transfer bus includes plural signal paths so ordered that each path is associated with one said digit position, and further comprising; A. a plurality of memory address words each having n bits including bits designating a page address, a sector address within a page, and a word address within a sector; B. an instruction word having m bits including bits designated a word, an operation code and an FSZ bit, said FSZ bit designating the register source of a sector and page address; C. means for loading said program counter with one of said plurality of memory address words; D. means for loading said sector register with the page and sector bits of one of said plurality of memory address words; E. means for loading one of said plurality of memory address words into said noun register, including:

Claim 39

A processor as defined in claim 12 further comprising: A. means for loading selected sector address bits, independent of the sector address bits in said program counter and in said sector register, into said noun register; and B. means for maintaining the bits loaded in said program counter and in said sector register undisturbed during said loading of said selected sector address bits.

Claim 40

A processor as defined in claim 12 further comprising: A. means for responding to a branch instruction of said operation code, said means for responding comprising:

Claim 41

A processor as defined in claim 12 further comprising: A. control and transfer means comprising:

Claim 42

A processor as defined in claim 12, further comprising: A. first gate means and second gate means for transferring respectively sector address bits and word address bits from said program counter to said noun register and B. control and transfer means comprising: