Peripheral interrupt apparatus for digital computer system

Claim 2

A digital computer system, comprising a central processing unit; a plurality of peripheral devices; connecting circuitry extending between the central processing unit and each of the plurality of peripheral devices including an address bus, a data bus and a single interrupt request line; a permanent unique address source associated with each peripheral device; a comparator associated with each device connected to the address bus and to the address source and operative to provide a signal to the device on the occurrence of identity between an address transmitted on the address bus and the address source of that device; means within the peripheral device for generating an interrupt request signal on the interrupt request line; means in the peripheral device operative upon receiving an interrupt acknowledge signal from the central processing unit on said connecting circuitry following the transmission of an interrupt request signal by that device for connecting said address source to the address bus; and circuitry for providing signals relating to the status of circuitry on the card to the data bus in response to the simultaneous occurrence of said signal from the comparator and an interrupt acknowledge signal so as to simultaneously identify the interrupting peripheral device and provide additional information encoded in the last said signal to the central processing unit.

Claim 3

The system of claim 1 wherein the provision of said signals to said data bus is further conditioned by a status request signal generated within the peripheral device in response to an interrupt acknowledge signal received from the central processing unit.

Claim 4

The system of claim 1 wherein each peripheral device is connected to said buses through circuitry formed on a plug-in circuit card and each of said circuit cards is electrically connected to back plane wiring associated with a chassis.

Claim 5

The system of claim 3 wherein said unique address source for each peripheral is at least partially constituted by said back plane wiring.

Claim 6

The system of claim 4 wherein at least a portion of the unique address source is constituted by switches associated with said chassis and all of the circuit boards associated with said chassis share such common address parts.

Claim 7

A computer system, comprising: a central processing unit; a plurality of peripheral devices; a plurality of circuit cards, one connected to each peripheral device; a chassis having back plane wiring and connectors adapted to receive a plurality of said circuit boards; address storage means associated with said chassis operative to provide each circuit board plugged into the chassis with a unique digital address; a bus connecting said central processing unit with said chassis and including an address section a data section and a single interrupt request line; comparator means formed on each circuit board and connected to the address section of the bus and to the address storage means and operative to provide an output signal upon identity occurring betweeN the contents of the address storage means and the address transmitted on the bus; circuitry on each circuit board for providing an interrupt request signal to the central processing unit over the bus; circuitry on each circuit board for connecting the address storage means to the address section of the bus upon receipt of an interrupt acknowledge signal from the central processing unit following the provision of an interrupt request signal by that circuit board; and circuitry on each board responsive to an output from the comparator and the simultaneous occurrence of an interrupt acknowledge signal to provide signals relating to the status of circuitry on the card to the bus.

Claim 8

A computer system, comprising: a central processing unit; a plurality of peripheral devices; a plurality of circuit cards, one connected to each peripheral device; a chassis having back plane wiring and connectors adapted to receive a plurality of said circuit boards; address storage means associated with said chassis operative to provide each circuit board plugged into the chassis with a unique digital address; a bus connecting said central processing unit with said chassis and including an address section a data section and a single interrupt request line; comparator means formed on each circuit board and connected to the address section of the bus and to the address storage means and operative to provide an output signal upon identity occurring betweeN the contents of the address storage means and the address transmitted on the bus; circuitry on each circuit board for providing an interrupt request signal to the central processing unit over the bus; circuitry on each circuit board for connecting the address storage means to the address section of the bus upon receipt of an interrupt acknowledge signal from the central processing unit following the provision of an interrupt request signal by that circuit board; and circuitry on each board responsive to an output from the comparator and the simultaneous occurrence of an interrupt acknowledge signal to provide signals relating to the status of circuitry on the card to the bus.

Claim 9

The computer system of claim 6 including a two-state device associated with each circuit board and adapted to be set into a first condition upon transmission of an interrupt request signal by that board, and to be reset into a second condition upon receipt of an interrupt acknowledge signal from the computer; and circuitry associated with each board conditioning the connection of the address storage means to the address section of the bus upon the status of said two-state device.

Claim 10

The system of claim 7 wherein the bus includes conductors interconnecting each adjacent circuit card, said conductors being operative to receive and pass along to the next circuit card an interrupt acknowledge signal from the computer if its two-state device is in a first condition and operative to provide an enabling signal to additional circuitry formed on the card if the output of the two-state device is in a second condition.