Data communication system including address-generating means and method

Claim 2

A data communication system comprising: a data processor; a memory in communication with said processor, said memory having a plurality of individually addressable storage cells, each of said cells being capable of holding a data word; a plurality of external devices for receiving data words retrieved from said memory; and means intermediate said memory and said external devices for supplying addresses to said memory for the retrieval of data words therefrom; means for directing the transfer of data words retrieved to individual ones of said external devices, said means including a plurality of line units for transferring retrieved data words to said devices, selector means for successively selecting individual ones of said plurality of line units, and addressgenerating means for generating cell addresses of said individually addressable storage cells to be supplied to said memory, said address-generating means responsive to the selection of one of said line units to form a first portion of said cell address and responsive to the last previouslY received data word by the selected line unit to form a second portion of said cell address.

Claim 3

A data communication system comprising: a data processor; a memory in communication with said processor, said memory having a plurality of individually addressable storage cells, each of said cells being capable of holding a data word; a plurality of external devices for receiving data words retrieved from said memory; and means intermediate said memory and said external devices for supplying addresses to said memory for the retrieval of data words therefrom; means for directing the transfer of data words retrieved to individual ones of said external devices, said means including a plurality of line units for transferring retrieved information items to said devices and for providing a first signal indicative of each receipt of a data word, selector means for successively selecting individual ones of said plurality of line units and for providing a second signal indicative of the line unit selected, and address-generating means for generating cell addresses of said individually addressable storage cells to be supplied to said memory, said address generating means responsive to said first and said second signals to form respectively first and second portions of said cell address.

Claim 4

A data communication system comprising: a data processor; a memory in communication with said processor, said memory having a plurality of individually addressable storage cells, each of said cells being capable of holding a data word; a plurality of external devices for receiving data words retrieved from said memory; and means intermediate said memory and said external devices for supplying addresses to said memory for the retrieval of data words therefrom; means for directing the transfer of data words retrieved to individual ones of said external devices, said means including a plurality of line units for transferring retrieved information items to said devices and for providing a first signal indicative of each receipt of a data word, selector means for successively selecting individual ones of said plurality of line units and for providing a second signal indicative of the line unit selected, and address-generating means for generating cell addresses of said individually addressable storage cells to be supplied to said memory, said address generating means responsive to said first and said second signals to form respectively first and second portions of said cell address.

Claim 7

An information transfer controller and director, for servicing portions of a data processor working store memory having queues of messages for a network of communications data terminals, comprising: a plurality of character register means for transmission and reception of character data to and from data terminals; a plurality of word registers, each word register being connected to a plurality of said character register means, for holding data from a memory cell and selectively transferring character data to said character registers; selector means, connected to said word register means, for selectively transferring data to said character register means; base register means for holding data representing an address in working store memory of a queue of messages; a plurality of word count means, connected to said selector means, for holding data representing current message word pointer information; address-generating means, connected to said base register means, and said word count means, for forming an address of a cell in working store memory for transfer of data to said word registers; transmit control means, connected to said word registers and said address-generating means, for successively selecting said word registers to receive data from a memory and applying signals representing this selection to said address-generating means.

Claim 8

An information transfer controller and director, for servicing portions of a data processor working store memory having queues of messages for a network of communications data terminals, comprising: a plurality of character register means for transmission and reception of character data to and from data terminals; a plurality of word registers, each word register being connected to a plurality of said character register means, for holding data from a memory cell and selectively transferring character data to said character registers; selector means, connected to said word register means, for selectively transferring data to said character register means; base register means for holding data representing an address in working store memory of a queue of messages; a plurality of word count means, connected to said selector means, for holding data representing current message word pointer information; address-generating means, connected to said base register means, and said word count means, for forming an address of a cell in working store memory for transfer of data to said word registers; transmit control means, connected to said word registers and said address-generating means, for successively selecting said word registers to receive data from a memory and applying signals representing this selection to said address-generating means.

Claim 9

An information transfer controller and director, for servicing portions of a data processor working store memory having queues of messages for a network of communications data terminals, comprising: a plurality of receive scanners, each scanner including an incoming character register, for successively receiving character data from a plurality of data terminals; a plurality of receive line units, each unit connected to a plurality of said receive scanners, for selectively receiving character daTa, each said receive line unit including a word register for holding a plurality of data characters from said receive scanners, selector means for selecting said receive scanners, control means for combining a plurality of data characters for said word register, message location means for holding data representing word pointer information; address-generating means, connected to said control means and said message location means, for forming an address of a cell in working store memory for transfer of word data from said receive line units.

Claim 10

An information transfer controller and director, for servicing portions of a data processor working store memory having queues of messages for a network of communications data terminals, comprising: a plurality of receive scanners, each scanner including an incoming character register, for successively receiving character data from a plurality of data terminals; a plurality of receive line units, each unit connected to a plurality of said receive scanners, for selectively receiving character daTa, each said receive line unit including a word register for holding a plurality of data characters from said receive scanners, selector means for selecting said receive scanners, control means for combining a plurality of data characters for said word register, message location means for holding data representing word pointer information; address-generating means, connected to said control means and said message location means, for forming an address of a cell in working store memory for transfer of word data from said receive line units.