Abstract An interface adaptor suitable for use in a microprocessor system includes an input register coupled to a bidirectional data bus of the microprocessor system. The interface adaptor includes a plurality of registers, including a control register and a data register, coupled to the input register by means of an internal input bus. Each of the plurality of registers includes flip-flops which are coupled as slave flip-flops to corresponding flip-flops of the input register. The corresponding flip-flops of the input register function as master flip-flops. The interface adaptor also includes register selection logic circuitry for selecting one of the plurality of registers by electrically coupling its slave flip-flop to the corresponding master flip-flops of the input register.
A digital system including a digital storage circuit including a master flip-flop coupled to an input data source and further including a slave flip-flop coupled to said master flip-flop and further including clock selection means coupled to said master and slave flip-flops for controlling transfer of stored data from said master flip-flop to said slave flip-flop and an additional slave flip-flop coupled to said master flip-flop in parallel to said slave flip-flop, said clock selection means also connected to said additional slave flip-flop for controlling the transfer of stored data from said master flip-flop to said additional slave flip-flop.
Claim 2
Dependent Claim
99 words
A digital system including a digital storage circuit including a master flip-flop coupled to an input data source and further including a slave flip-flop coupled to said master flip-flop and further including clock selection means coupled to said master and slave flip-flops for controlling transfer of stored data from said master flip-flop to said slave flip-flop and an additional slave flip-flop coupled to said master flip-flop in parallel to said slave flip-flop, said clock selection means also connected to said additional slave flip-flop for controlling the transfer of stored data from said master flip-flop to said additional slave flip-flop.
Claim 3
Dependent Claim
23 words
A digital system as recited in claim 1 wherein said master flip-flop is a stage of an input register of an interface adaptor.
Claim 4
Dependent Claim
38 words
A digital system as recited in claim 2 wherein said slave flip-flop is a register stage of a first control register of said interface adaptor; and said additional slave flip-flop is a data register of said interface adaptor.
Claim 5
Dependent Claim
48 words
A digital system as recited in claim 2 wherein said interface adaptor further includes clocked gating circuit means for selecting said additonal slave flip-flop as the destination for data stored in said master flip-flop, said clocked gating means being coupled to said master flip-flop and said slave flip-flop.