Dual port memory circuit

Claim 2

A dual port memory comprising a memory cell array including memory cells arranged in rows and columns; a random access peripheral circuit for performing a random access operation with respect to said cell array in response to row and column address information; and a serial access peripheral circuit performing consecutive access operations with respect to the columns of said array in response to shift pulses; said serial access circuit including a selection circuit for selecting one of said columns to be accessed, a counter circuit, means responsive to the output of said counter circuit for controlling said selection circuit, means for setting the counting value of said counter at an optional value and means for advancing the state of said counter circuit in response to said shift pulses.

Claim 3

The memory according to Claim 1, wherein said setting means includes a first transfer circuit for operatively applying the column address information to said counter circuit thereby to determine the state of said counter circuit.

Claim 4

The memory according to Claim 1, further comprising a plurality of data store circuits, each of said data store circuits operatively storing data on the associated one of said columns.

Claim 5

The memory according to Claim 3, further comprising a second transfer circuit coupled between said columns of said array and said data store circuits for operatively connecting the data on said columns to said data store circuits.

Claim 6

The memory according to Claim 1, wherein said selection circuit includes a decoding circuit for decoding the state of said counter circuit.

Claim 7

The memory according to Claim 1, wherein said setting means sets said counter circuit at the optional value during a period when said shift pulse is at an inactive level.

Claim 8

A dual port memory comprising: a memory array including a matrix of memory cells arranged at the intersections of word lines and digit lines; a random access circuit for effecting a write operation and a read operation randomly to and from said array in response to row address signals and column address signals; a data hold circuit including a plurality of storage units, a plurality of first transfer gates each coupled between an associated one of said digit lines and an associated one of said storage units; a counter circuit which increases its count value in response to shift pulses, a plurality of second transfer gates adapted to operatively supply said column address signal to said counter circuit; a selection circuit responsive to the output of said counter circuit for selectively outputting data stored in the storage unit defined by the count in said counter circuit, means for controlling the counting operation of said counter circuit; and means for operatively enabling said first and second transfer gates in response to a transfer control signal.

Claim 9

A dual port memory comprising: a memory array including a matrix of memory cells arranged at the intersections of word lines and digit lines; a random access circuit for effecting a write operation and a read operation randomly to and from said array in response to row address signals and column address signals; a data hold circuit including a plurality of storage units, a plurality of first transfer gates each coupled between an associated one of said digit lines and an associated one of said storage units; a counter circuit which increases its count value in response to shift pulses, a plurality of second transfer gates adapted to operatively supply said column address signal to said counter circuit; a selection circuit responsive to the output of said counter circuit for selectively outputting data stored in the storage unit defined by the count in said counter circuit, means for controlling the counting operation of said counter circuit; and means for operatively enabling said first and second transfer gates in response to a transfer control signal.

Claim 10

The memory according to Claim 7, wherein said transfer control signal is energized during a period that said shift pulses are at an inactive level.

Claim 11

The memory according to Claim 7, wherein each of said storage units includes a flip-flop.

Claim 12

The memory according to Claim 7, wherein said random access circuit incorporates the row address signals and the column address signals in response to a row address strobe signal and a column strobe signal, respectively.