Digital storage

Claim 2

1 A memory for storing a plurality of digital words each having digits stored in a row of memory locations, like digits in a row of memory locations, like digits of the words forming columns, the digital words being transferred to and from the memory locations through a plurality of sense amplifiers (17;82;101), characterised by a row buffer register means (25;47 to 62;80;91 to 93) having a plurality of parallel connections from the sense amplifiers, and means (26,27;84,89,88;98) to enable the row buffer register means to transfer data to an output port (24;63 to 78;85;95) independent of data transfer to or from memory locations.

Claim 3

2 A memory according to claim 1, in which the row buffer register means is a shift register having an output connected only to the output port, a data transfer port connected to enable the shift register to read and store data provided by the sense amplifiers, and a clock input port for serially gating each data bit stored in the register to the output port.

Claim 4

3 A memory according to claim 1 or 2, having a primary input/output port (23) for transferring data to and from the memory locations.

Claim 5

4 A memory according to claim 3, in which the output port is part of a secondary input/output port for transferring data, the register means is bidirectional for receiving data from the memory locations, or from the secondary input/output port, control means is provided for controlling the transfer of data between the register means and the memory locations, transferring data from the memory locations to the register means in response to a first control signal, and transferring such data to the secondary input/output port in response to a second control signal, and transferring data from the secondary port to the register means, and from the register means to the memory locations in response to third and fourth control signals, respectively, whereby data may be transferred between the register means and the secondary port independent of data transferred between the primary port and the memory locations.

Claim 6

5 A memory according to claim 4, in which the bidirectional register means comprises a first master/slave register combination, the slave portion being serially connected to provide data to the secondary port, the master portion being connected to receive in parallel data from the memory locations; and a second master/slave register combination, the master portion being connected to receive data from the secondary port, and the slave portion being connected to transfer data from the associated master portion to the memory locations.

Claim 7

6 A memory according to claim 3, in which a decoder means is connected to address the buffer register means in response to an address signal, the buffer register means providing a serial data stream of data bits identified by the address signal to the secondary port.

Claim 8

7 A memory according to claim 6, in which the decoder means provides decoding of a portion of the bits in the row buffer register means.

Claim 9

8 A memory according to any preceding claim, which is a random access memory.

Claim 10

9 A CRT display system in which individual data bits are generated during the scanning of a CRT screen, the data bits defining a pixel for display during scanning, and being stored and read out for display, comprising a plurality of random access memories (31 to 46) each according to claim 8 and comprising a plurality of addressable storage locations, arranged in columns and rows, a primary input/output port for transferring pixel data to and from the memory locations, a row buffer register (47.....62) connected to receive data from an addressed row of memory locations, a secondary port (63.....78) connected to receive data from the row buffer register, and first and second terminals for supplying first and second control signals to the row buffer register, the first control signal enabling the row register to receive data, the second control signal transferring the row buffer, register data to the secondary port, a shift register (79) having parallel inputs connected to the secondary ports of the memories, and means for shifting the contents of the shift register at a first rate related to the scan rate, and for transferring data from each of the row buffer registers at a second slower rate, whereby the shift register is continuously updated with new pixel data while forming a data stream of pixel data for display.