Program counter update mechanism

Claim 3

The apparatus of claim 1 further comprising a plurality of storage locations for storing the less significant first program counter portion and the carry signal, each storage location corresponding to each stage of the pipeline and being coupled to the first program counter circuit and the execute program counter circuit.

Claim 4

The apparatus of claim 1 wherein the more significant program counter value generator circuit includes an incrementer circuit, the incrementer circuit receiving the more significant bits of a present program counter value and an increment signal and providing a more significant portion of a next program counter value.

Claim 5

The apparatus of claim 3 wherein the more significant program counter value generator circuit includes a carry selector circuit, the carry selector circuit receiving a carry signal and providing the increment signal based upon the carry signal.

Claim 6

A microprocessor apparatus having a pipeline for processing instructions, the microprocessor apparatus comprising: a microprocessor core, the microprocessor core including a functional unit for executing instructions, a first program counter circuit for providing a first program counter value having a more significant first program counter portion, a less significant first program counter portion and a first carry signal, the first counter value representing a program count value of a retrieved instruction; and an execute program counter circuit for receiving the less significant first program counter portion and the first carry signal and generating an execute program counter value using the less significant first program counter portion, the execute program counter circuit being coupled to the first program counter circuit, the execute program counter value representing a program count value of an executed instruction, the functional unit using the execute program counter value when executing instructions, the first program counter circuit includes a less significant program counter value generator circuit and a more significant program counter value generator circuit; the less significant program counter value generator circuit includes a plurality of adder circuits for providing a plurality of sequential next program counter values, each adder circuit receiving a less significant portion of a present program counter value and an instruction length value of a respective sequential instruction in the pipeline and adding the less significant portion of the present program counter value to the instruction length value to provide a respective less significant portion of one of the next program counter values and a corresponding carry signal.

Claim 7

A microprocessor apparatus having a pipeline for processing instructions, the microprocessor apparatus comprising: a microprocessor core, the microprocessor core including a functional unit for executing instructions, a first program counter circuit for providing a first program counter value having a more significant first program counter portion, a less significant first program counter portion and a first carry signal, the first counter value representing a program count value of a retrieved instruction; and an execute program counter circuit for receiving the less significant first program counter portion and the first carry signal and generating an execute program counter value using the less significant first program counter portion, the execute program counter circuit being coupled to the first program counter circuit, the execute program counter value representing a program count value of an executed instruction, the functional unit using the execute program counter value when executing instructions, the first program counter circuit includes a less significant program counter value generator circuit and a more significant program counter value generator circuit; the less significant program counter value generator circuit includes a plurality of adder circuits for providing a plurality of sequential next program counter values, each adder circuit receiving a less significant portion of a present program counter value and an instruction length value of a respective sequential instruction in the pipeline and adding the less significant portion of the present program counter value to the instruction length value to provide a respective less significant portion of one of the next program counter values and a corresponding carry signal.

Claim 8

The apparatus of claim 5 further comprising a plurality of storage locations for storing the less significant first program counter portion and the carry signal, each storage location corresponding to each stage of the pipeline and being coupled to the first program counter circuit and the execute program counter circuit.

Claim 9

The apparatus of claim 5 wherein the more significant program counter value generator circuit includes an incrementer circuit, the incrementer circuit receiving the more significant bits of a present program counter value and an increment signal and providing a more significant portion of a next program counter value.

Claim 10

The apparatus of claim 11 wherein the more significant program counter value generator circuit includes a carry selector circuit, the carry selector circuit receiving a carry signal and providing the increment signal based upon the carry signal.