US5465373A
Expired / Lapsed
US
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Method and system for single cycle dispatch of multiple instructions in a superscalar processor system
Assignee: International Business Machines Corp
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Filing: 1993-01-08
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Granted: 1995-11-07
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Expires: 2013-01-08
Abstract
Abstract A method and system for permitting single cycle instruction dispatch in a superscalar processor system which dispatches multiple instructions simultaneously to a group of execution units for execution and placement of results thereof within specified general purpose registers. Each instruction generally includes at least one source operand and one destination operand. A plurality of intermediate storage buffers are provided and each time an instruction is dispatched to an available execution unit, a particular one of the intermediate storage buffers is assigned to any destination operand within the dispatched instruction, permitting the instruction to be dispatched within a single cycle by eliminating any requirement for determining and selecting the specified general purpose register or a designated alternate general purpose register.
Inventors
- 👤 James A. Kahle
- 👤 Chin-Cheng Kau
- 👤 David S. Levitan
- 👤 Aubrey D. Ogden
- 👤 Ali A. Poursepanj
- 👤 Paul K.-G. Tu
- 👤 Donald E. Waldecker
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 01:01
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3836; G06F9/3838; G06F9/384
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
242 words
A method for enhanced instruction dispatch efficiency in a superscalar processor system capable of simultaneously dispatching multiple scalar instructions to a plurality of execution units during each single processor cycle, each of said multiple scalar instructions including at least one source operand and one destination operand, said method comprising the steps of: providing a plurality of intermediate storage buffers within said superscalar processor system; during said single processor cycle: determining if an appropriate one of said plurality of execution units is available for execution of a selected one of said multiple scalar instructions; determining if a destination operand within a preceding one of said multiple scalar instructions is equal to a source operand within said selected one of said multiple scalar instructions; assigning a particular one of said plurality of intermediate storage buffers to said destination operand within said selected one of said multiple scalar instructions; and dispatching said selected one of said multiple scalar instructions to said appropriate one of said plurality of execution units in response to said availability thereof, said assignment of said particular one of said plurality of intermediate storage buffers to said destination operand and an assignment of another one of said plurality of intermediate storage buffers to said destination operand within said preceding one of said multiple scalar instructions wherein results of execution of said selected one of said multiple scalar instructions may be written to said particular one of said plurality of intermediate storage buffers.
Claim 2
Independent Claim
242 words
A method for enhanced instruction dispatch efficiency in a superscalar processor system capable of simultaneously dispatching multiple scalar instructions to a plurality of execution units during each single processor cycle, each of said multiple scalar instructions including at least one source operand and one destination operand, said method comprising the steps of: providing a plurality of intermediate storage buffers within said superscalar processor system; during said single processor cycle: determining if an appropriate one of said plurality of execution units is available for execution of a selected one of said multiple scalar instructions; determining if a destination operand within a preceding one of said multiple scalar instructions is equal to a source operand within said selected one of said multiple scalar instructions; assigning a particular one of said plurality of intermediate storage buffers to said destination operand within said selected one of said multiple scalar instructions; and dispatching said selected one of said multiple scalar instructions to said appropriate one of said plurality of execution units in response to said availability thereof, said assignment of said particular one of said plurality of intermediate storage buffers to said destination operand and an assignment of another one of said plurality of intermediate storage buffers to said destination operand within said preceding one of said multiple scalar instructions wherein results of execution of said selected one of said multiple scalar instructions may be written to said particular one of said plurality of intermediate storage buffers.
Claim 3
Dependent Claim
55 words
The method for enhanced instruction dispatch efficiency in a superscalar processor system according to claim 1, further including the step of transferring said results of execution of said selected one of said multiple scalar instructions from said particular one of said plurality of intermediate storage buffers to a general purpose register on an opportunistic basis.
Claim 4
Independent Claim
256 words
A system for enhanced instruction dispatch efficiency in a superscalar processor system capable of simultaneously dispatching multiple scalar instructions to a plurality of execution units during each single processor cycle, each of said multiple scalar instructions including at least one source operand and one destination operand, said system comprising: a plurality of intermediate storage buffers within said superscalar processor system; means for determining if an appropriate one of said plurality of execution units is available for execution of a selected one of said multiple scalar instructions during said single processor cycle; means for determining if a destination operand within a preceding one of said multiple scalar instructions is equal to a source operand within said selected one of said multiple scalar instructions; means for assigning a particular one of said plurality of intermediate storage buffers to said destination operand within said selected one of said multiple scalar instructions during said single processor cycle; and means for dispatching said selected one of said multiple scalar instructions to said appropriate one of said plurality of execution units in response to said availability thereof, said assignment of said particular one of said plurality of intermediate storage buffers to said destination operand and an assignment of another one of said plurality of intermediate storage buffers to said destination operand within said preceding one of said multiple scalar instructions during said single processor cycle wherein results of execution of said selected one of said multiple scalar instructions may be written to said particular one of said plurality of intermediate storage buffers.
Claim 5
Independent Claim
256 words
A system for enhanced instruction dispatch efficiency in a superscalar processor system capable of simultaneously dispatching multiple scalar instructions to a plurality of execution units during each single processor cycle, each of said multiple scalar instructions including at least one source operand and one destination operand, said system comprising: a plurality of intermediate storage buffers within said superscalar processor system; means for determining if an appropriate one of said plurality of execution units is available for execution of a selected one of said multiple scalar instructions during said single processor cycle; means for determining if a destination operand within a preceding one of said multiple scalar instructions is equal to a source operand within said selected one of said multiple scalar instructions; means for assigning a particular one of said plurality of intermediate storage buffers to said destination operand within said selected one of said multiple scalar instructions during said single processor cycle; and means for dispatching said selected one of said multiple scalar instructions to said appropriate one of said plurality of execution units in response to said availability thereof, said assignment of said particular one of said plurality of intermediate storage buffers to said destination operand and an assignment of another one of said plurality of intermediate storage buffers to said destination operand within said preceding one of said multiple scalar instructions during said single processor cycle wherein results of execution of said selected one of said multiple scalar instructions may be written to said particular one of said plurality of intermediate storage buffers.
Claim 6
Dependent Claim
54 words
The system for enhanced instruction dispatch efficiency in a superscalar processor system according to claim 3, further including means for transferring said results of execution of said selected one of said multiple scalar instructions from said particular one of said plurality of intermediate storage buffers to a general purpose register on an opportunistic basis.
Claim 7
Independent Claim
258 words
A method for enhanced instruction dispatch efficiency in a superscalar processor system capable of simultaneously dispatching multiple scalar instructions to a plurality of execution units during each single processor cycle, each of said multiple scalar instructions including at least one source operand and one destination operand, said method comprising the steps of: providing a plurality of intermediate storage buffers within said superscalar processor system; during said single processor cycle: determining if an appropriate one of said plurality of execution units is available for execution of a selected one of said multiple scalar instructions; determining if a destination operand within a preceding one of said multiple scalar instructions is equal to a source operand within said selected one of said multiple scalar instructions; assigning a particular one of said plurality of intermediate storage buffers to said destination operand within said selected one of said multiple scalar instructions; specifying said at least one source operand; and dispatching said selected one of said multiple scalar instructions to said appropriate one of said plurality of execution units in response to said availability thereof, said assignment of said particular one of said plurality of intermediate storage buffers to said destination operand, an assignment of another one of said plurality of intermediate storage buffers to said destination operand within said preceding one of said multiple scalar instructions and said specifying of said at least one source operand, wherein results of execution of said selected one of said multiple scalar instructions may be written to said particular one of said plurality of intermediate storage buffers.
Claim 8
Independent Claim
258 words
A method for enhanced instruction dispatch efficiency in a superscalar processor system capable of simultaneously dispatching multiple scalar instructions to a plurality of execution units during each single processor cycle, each of said multiple scalar instructions including at least one source operand and one destination operand, said method comprising the steps of: providing a plurality of intermediate storage buffers within said superscalar processor system; during said single processor cycle: determining if an appropriate one of said plurality of execution units is available for execution of a selected one of said multiple scalar instructions; determining if a destination operand within a preceding one of said multiple scalar instructions is equal to a source operand within said selected one of said multiple scalar instructions; assigning a particular one of said plurality of intermediate storage buffers to said destination operand within said selected one of said multiple scalar instructions; specifying said at least one source operand; and dispatching said selected one of said multiple scalar instructions to said appropriate one of said plurality of execution units in response to said availability thereof, said assignment of said particular one of said plurality of intermediate storage buffers to said destination operand, an assignment of another one of said plurality of intermediate storage buffers to said destination operand within said preceding one of said multiple scalar instructions and said specifying of said at least one source operand, wherein results of execution of said selected one of said multiple scalar instructions may be written to said particular one of said plurality of intermediate storage buffers.
Claim 9
Dependent Claim
55 words
The method for enhanced instruction dispatch efficiency in a superscalar processor system according to claim 5, wherein said step of specifying said at least one source operand comprises the step of designating a selected one of said plurality of intermediate storage buffers to be utilized as a location for said at least one source operand.
Claim 10
Dependent Claim
38 words
The method for enhanced instruction dispatch efficiency in a superscalar processor system according to claim 5, comprising the step of designating a general purpose register to be utilized as a location for said at least one source operand.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-11-06 | 1999-05-08 | 1999-11-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-11-06 | 2003-05-08 | 2003-11-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-11-06 | 2007-05-08 | 2007-11-07 | $7700.00 | Window Closed / Lapsed |