EP0180005A2
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EP
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Dual incrementor
Assignee: International Business Machines Corp
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Filing: 1985-09-03
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Granted: —
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Expires: 2005-09-03
Abstract
Abstract A "lookback" carry function is implemented in a binary incrementor. In contrast to conventional lookahead carry functions, the present "lookback" carry function implements an actual carry during the incrementing operation. After the carry function has been implemented at each register position, a subsequent determination is made as to whether each carry function was a valid one and should have been carried out. With respect to any carry functions which were not valid, subsequent circuitry will eliminate such carries to leave the appropriate carry pattern in each position of the register. In order for a carry to be considered valid, the incrementation of all bits of a lower order must have resulted in a carryout.
Inventors
- 👤 Abraham Torres
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-02 14:36
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/38; G06F7/48; G06F7/50; G06F7/505; G06F7/5055; G06F9/00; G06F9/06; G06F9/30; G06F9/32; G06F9/321
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
89 words
A binary incrementor for incrementing a binary number, having a plurality of bits, input thereto, characterized in that it comprises : first means for incrementing a first section of an inputted binary number, thereby producing an incremented first section; second means for incrementing a second section of said inputted binary number, said second means producing a signal if the incrementation of said second section results in a carryout; and, means connected to said first and said second means for outputting said incremented first section upon receipt of said signal.
Claim 2
Dependent Claim
89 words
A binary incrementor for incrementing a binary number, having a plurality of bits, input thereto, characterized in that it comprises : first means for incrementing a first section of an inputted binary number, thereby producing an incremented first section; second means for incrementing a second section of said inputted binary number, said second means producing a signal if the incrementation of said second section results in a carryout; and, means connected to said first and said second means for outputting said incremented first section upon receipt of said signal.
Claim 3
Dependent Claim
31 words
A binary incrementor according to Claim 1 wherein said first means comprises a first stage for generating at least one carry bit from a plurality of bits in said first section.
Claim 4
Dependent Claim
37 words
A binary incrementor according to Claim 2 wherein said first means further comprises a second stage for generating a sum from said at least one carry bit and from said plurality of bits in said first section.
Claim 5
Dependent Claim
53 words
A binary incrementor according to Claim 2 wherein said first stage comprises a NOR gate implementing the logical relationship, where C j , and C j+1 are carry bits of bits j and j+l, respectively, of said plurality of bits, and wherein P . is the jth bit of said plurality of bits.
Claim 6
Dependent Claim
34 words
A binary incrementor according to Claim 4 wherein said second stage comprises an EXCLUSIVE OR gate implementing the logical relationship, wherein SUM. is the sum of the jth bit of said plurality of bits.
Claim 7
Dependent Claim
36 words
A binary incrementor according to any one of the preceding claims wherein said means comprises a plurality of inputs for receiving said first section of said inputted binary number and for receiving said incremented first section.
Claim 8
Dependent Claim
27 words
A binary incrementor according to Claim 6 wherein said first section and said incremented first section are divided into a plurality of corresponding bytes of ascending order.
Claim 9
Dependent Claim
69 words
A binary incrementor according to Claim 7 wherein said means outputs a byte of said incremented first section subsequent to a carryout being produced by both the incrementation of each and every byte of descending order and by said second means, and wherein said means outputs a byte of said first section subsequent to no carryout being produced by any byte of descending order or by said second means.
Claim 10
Independent Claim
67 words
A method for incrementing a binary number having a plurality of bits, characterized in that it comprises : incrementing a first section of an inputted binary number to produce an incremented first section; incrementing a second section of said inputted binary number; signalling the production of a carryout after incrementing said second section; and, outputting said incremented first section subsequent to signalling the production of a carryout.
Claim 11
Independent Claim
67 words
A method for incrementing a binary number having a plurality of bits, characterized in that it comprises : incrementing a first section of an inputted binary number to produce an incremented first section; incrementing a second section of said inputted binary number; signalling the production of a carryout after incrementing said second section; and, outputting said incremented first section subsequent to signalling the production of a carryout.
Claim 12
Dependent Claim
54 words
A method according to Claim 9, wherein the step of incrementing said first section comprises the substeps of: generating at least one carry bit from a plurality of bits in said first section; and, generating a sum from said at least one carry bit and from said plurality of bits in said first section.
Claim 13
Dependent Claim
126 words
A binary incrementor for generating at least one new address from a current address, each address represented by a binary number having at least two sections, said binary incrementor being characterized in that it comprises: first means for incrementing a first section of said current address, thereby producing an incremented first section of said current address; second means for incrementing a second section of said current address, thereby producing an incremented second section, said second means signalling the generation of a carryout after incrementing said second section; and, means for outputting said incremented first section upon generation of a carryout signal by said second means, said means outputting said first section of said current address subsequent to no carryout signal being generated by said second means.
Claim 14
Dependent Claim
126 words
A binary incrementor for generating at least one new address from a current address, each address represented by a binary number having at least two sections, said binary incrementor being characterized in that it comprises: first means for incrementing a first section of said current address, thereby producing an incremented first section of said current address; second means for incrementing a second section of said current address, thereby producing an incremented second section, said second means signalling the generation of a carryout after incrementing said second section; and, means for outputting said incremented first section upon generation of a carryout signal by said second means, said means outputting said first section of said current address subsequent to no carryout signal being generated by said second means.
Claim 15
Dependent Claim
37 words
A binary incrementor according to Claim 11 further comprising means for combining a first section of said current address from said outputting means with the incremented second section from said second means to produce a new address.
Claim 16
Dependent Claim
81 words
A binary incrementor according to Claims 11 or 12 further comprising: third means for incrementing said second section of said current address, thereby producing an incremented third section, said third means signaling the generation of a carryout after incrementing said second section; and, means for outputting said incremented first section upon generation of a carryout signal by said third means, said means outputting said first section of said current address subsequent to no carryout signal being generated by said third means.
Claim 17
Dependent Claim
38 words
A binary incrementor according to Claim 13 further comprising means for combining a first section of said current address from said outputting means with the incremented third section from said third means to produce a second new address.
References Cited (Backward Citations)
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