Patent US5535509A successfully refreshed from Google Patents.
US5535509A
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US
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Method of making a lead on chip (LOC) semiconductor device
Assignee: Renesas Electronics Corp
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Filing: 1994-10-19
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Granted: 1996-07-16
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Expires: 2014-10-19
Abstract
Abstract A semiconductor device including a lead on chip structure employs two frames. One of the frames includes a die pad and an outer frame portion and the other frame includes a plurality of leads and an outer lead portion. After a semiconductor chip is die bonded to the die pad, the two frames are connected to each other with the leads extending across the semiconductor chip. Slits within the second frame provide access to parts of the outer frame of the first frame and the first frame is severed at those slits. The severed portions of the first frame are removed after which the leads of the second frame are connected by wire bonding to the semiconductor chip. Finally, the semiconductor chip, the remaining part of the first frame, and the second frame are encapsulated in a resin with leads extending from the resin. The remaining parts of the outer frame of the second frame are removed by cutting and the exposed leads outside the resin are formed into a desired shape.
Inventors
- 👤 Yoshihiro Tomita
- 👤 Naoto Ueda
- 👤 Yoshirou Nishinaka
- 👤 Shunichi Abe
- 👤 Hideyuki Ichiyama
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 08:03
CPC Classifications
H; H10; H10W; H10W70/00; H10W70/01; H10W70/04; H10W70/048; H10W70/40; H10W70/411; H10W70/415; H10W70/421; H10W70/424; H10W70/427; H10W70/442; H10W74/00; H10W74/01; H10W74/016; H10W74/10; H10W90/00; H10W90/811; H10W72/00; H10W72/071; H10W72/073; H10W72/07331; H10W72/07336; H10W72/075; H10W72/07531; H10W72/07532; H10W72/07533; H10W72/30; H10W72/351; H10W72/353; H10W72/354; H10W72/50; H10W72/541; H10W72/5449; H10W72/547; H10W72/5473; H10W72/551; H10W72/552; H10W72/59; H10W72/851; H10W72/874; H10W72/884; H10W72/90; H10W72/931; H10W72/932; H10W72/941; H10W72/944; H10W72/9445; H10W72/951; H10W90/701; H10W90/731; H10W90/736; H10W90/751; H10W90/756; Y; Y10; Y10T; Y10T29/00; Y10T29/49; Y10T29/49002; Y10T29/49117; Y10T29/49121; Y10T29/49124; Y10T29/4913; Y10T29/49146; Y10T29/49169; Y10T29/49171; Y10T29/49172
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
313 words
A method for producing a semiconductor device having a lead on chip (LOC) structure using a first frame including an outer frame in a first plane and a die pad connected to the outer frame and displaced from the first plane, and a second frame comprising an outer lead frame, a plurality of leads extending inwardly from the outer lead frame, and frame-cutting slits in said outer lead frame of said second frame for cutting a portion of said first frame after said second frame is connected to said first frame, said method comprising, sequentially: die-bonding a semiconductor chip to said die pad of said first frame; connecting said second frame to said first frame with an inner lead portion of each of said leads extending across said semiconductor chip mounted on said die pad and with the slits in said second frame exposing parts of said outer frame of said first frame; cutting said exposed parts of said outer frame of said first frame at the frame-cutting slits of said second frame and removing said exposed parts of said outer frame of said first frame, leaving a remaining part of said first frame including said die pad connected to said second frame; wire-bonding wires between said semiconductor chip and said inner lead portions of said leads; encapsulating said semiconductor chip, said remaining part of said first frame including said die pad, said wires, and parts of said second frame in a resin body with an outer lead portion of each of said leads exposed outside of said resin body; plating said outer lead portions exposed outside of said resin body; cutting said outer lead frame of said second frame exposed outside of said resin body to separate said outer lead portions from each other; and deforming each of said outer lead portions exposed outside of said resin body into a desired shape.
Claim 2
Independent Claim
313 words
A method for producing a semiconductor device having a lead on chip (LOC) structure using a first frame including an outer frame in a first plane and a die pad connected to the outer frame and displaced from the first plane, and a second frame comprising an outer lead frame, a plurality of leads extending inwardly from the outer lead frame, and frame-cutting slits in said outer lead frame of said second frame for cutting a portion of said first frame after said second frame is connected to said first frame, said method comprising, sequentially: die-bonding a semiconductor chip to said die pad of said first frame; connecting said second frame to said first frame with an inner lead portion of each of said leads extending across said semiconductor chip mounted on said die pad and with the slits in said second frame exposing parts of said outer frame of said first frame; cutting said exposed parts of said outer frame of said first frame at the frame-cutting slits of said second frame and removing said exposed parts of said outer frame of said first frame, leaving a remaining part of said first frame including said die pad connected to said second frame; wire-bonding wires between said semiconductor chip and said inner lead portions of said leads; encapsulating said semiconductor chip, said remaining part of said first frame including said die pad, said wires, and parts of said second frame in a resin body with an outer lead portion of each of said leads exposed outside of said resin body; plating said outer lead portions exposed outside of said resin body; cutting said outer lead frame of said second frame exposed outside of said resin body to separate said outer lead portions from each other; and deforming each of said outer lead portions exposed outside of said resin body into a desired shape.
Claim 3
Dependent Claim
17 words
The method of claim 1 including connecting said second frame to said first frame by resistance welding.
Claim 4
Dependent Claim
35 words
The method of claim 1 including connecting said second frame to said first frame by applying an adhesive tape between said first and second frames and pressing said first and second frames against each other.
Claim 5
Dependent Claim
20 words
The method of claim 3 wherein said adhesive tape includes an adhesive on two opposite sides of said adhesive tape.
Claim 6
Dependent Claim
16 words
The method of claim 1 including connecting said second frame to said first frame by riveting.
Claim 7
Dependent Claim
63 words
The method of claim 1 including producing a projection extending from one of said first and second frames and forming a hole for receiving the projection in the other of said first and second frames and connecting said second frame to said first frame by inserting the projection into the hole and bending the projection to hold said first and second frames together.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-07-16 | 2000-01-15 | 2000-07-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-07-16 | 2004-01-15 | 2004-07-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-07-16 | 2008-01-15 | 2008-07-16 | $7700.00 | Window Closed / Lapsed |