Method and apparatus for reducing jitter in a phase locked loop circuit

Claim 1

A phase locked loop circuit comprising; a phase/frequency detector for comparing the difference in the phase/frequency of an input clock reference signal with an output clock signal and for providing a phase/frequency output comprised of increment and decrement signals, a charge pump coupled to said phase/frequency detector, for transferring said increment and decrement pulses to said charge pump, a loop filter coupled to said charge pump, for providing a current input to a current controlled oscillator, the current controlled oscillator providing an output current having a frequency, the frequency relating to the magnitude of the current input to the current controlled oscillator, and a jitter control circuit connected to said phase/frequency detector and to said charge pump; said jitter control circuit including a first circuit element directly connecting said charge pump to a first current source; a second circuit element connecting said charge pump to a second current source; a switch having open and closed positions in said second circuit element for connecting and disconnecting said second circuit element and said charge pump to and from each other; and an actuation circuit in circuit connection with said switch and for triggering operation of said switch in response to a predetermined phase relationship between said input clock reference signal and said output clock signal; said actuation circuit comprising: a phase lock signal input for receiving a phase lock signal; and a complementary follower circuit in circuit connection with said phase lock signal input and for isolating said phase lock signal input from said switch.