CMOS circuit providing 90 degree phase delay

Claim 2

In combination: phase shifter means responsive to a non-return-to-zero input data signal for providing a signal shifted in phase from said input data signal; means responsive to said input data signal and said phase shifted signal for generating a signal which includes a frequency component of an originating clock of said input data signal; a phase-locked loop responsive to said signal from said generating means, said loop comprising an oscillator providing an output synchronized to said frequency component of the originating clock; and said phase shifter means providing a delay in response to said phase-locked loop to provide a phase shift of 90° at the output frequency of said oscillator.

Claim 3

The combination recited in claim 1 wherein said generating means comprises an exclusive OR.

Claim 4

The combination recited in claim 2 wherein said phase-locked loop further comprises a phase detector responsive to said exclusive OR and the output of said oscillator, said oscillator being responsive to said phase detector.

Claim 5

The combination recited in claim 1 wherein said phase shifter means comprises a plurality of inverter delay circuits connected in a series.

Claim 6

The combination recited in claim 4 wherein the delay of each of said inverter delay circuits of said phase shifter means is responsive to a current in said phase-locked loop.

Claim 7

The combination recited in claim 5 wherein said oscillator comprises a ring oscillator comprising at plurality of inverter delay circuits connected in a ring.

Claim 8

The combination recited in claim 6 further comprising means for providing each of said inverter delay circuits of said phase shifter means with the same delay as each of said inverter delay circuits of said oscillator.

Claim 9

In combination: means responsive to an input data signal for providing an output signal shifted in phase from the input data signal; means for providing an exclusive OR signal in response to the input data signal and the phase shift signal; phase-locked loop means comprising an oscillator having an output synchronized to said exclusive OR signal; and means for slaving said phase shift means to said phase-locked loop means to provide a phase shift of 90° at the frequency of said oscillator output.

Claim 10

In combination: means responsive to an input data signal for providing an output signal shifted in phase from the input data signal; means for providing an exclusive OR signal in response to the input data signal and the phase shift signal; phase-locked loop means comprising an oscillator having an output synchronized to said exclusive OR signal; and means for slaving said phase shift means to said phase-locked loop means to provide a phase shift of 90° at the frequency of said oscillator output.

Claim 11

The combination recited in claim 8 wherein said phase shift means comprises a plurality of inverter delay circuits connected in a series.

Claim 12

The combination recited in claim 9 wherein said oscillator comprises a ring oscillator comprising a plurality of inverter delay circuits connected in a ring.

Claim 13

The combination recited in claim 10 wherein said slave means comprises means for controlling the delay of each of said inverter delay circuits of said phase shift means in accordance with the delays of each of said inverter delay circuits of said ring oscillator.

Claim 14

The combination recited in claim 11 wherein said controlling means comprises means for causing each of said inverter delay circuits of said phase shifter and said ring oscillator to be determined by a feedback current in said phase-locked loop.

Claim 15

The combination recited in claim 12 wherein said inverter delays circuits of said phase shift means and said oscillator are differential inverters.

Claim 16

The combination recited in claim 8 wherein said phase-locked loop means further comprises a phase detector responsive to the exclusive OR signal and the output of said oscillator, said oscillator being a current controlled oscillator responsive to said phase detector.

Claim 17

In combination: a phase shifter adapted to receive a non-return-to-zero input data signal and provide an output signal shifted in phase from the input data signal, said phase shifter comprising a plurality of delay circuits connected in a series; an exclusive OR responsive to the input data signal and the phase shifted signal from the phase shifter; a phase-locked loop comprising a ring oscillator for providing an output synchronized to an output of the exclusive OR, said ring oscillator comprising a plurality of delay circuits connected in a loop; and means for operating the delay circuits of said phase shifter in accordance with the delays of the delay circuits of said ring oscillator to provide a 90° phase shift at the frequency of said output of said ring oscillator.

Claim 18

In combination: a phase shifter adapted to receive a non-return-to-zero input data signal and provide an output signal shifted in phase from the input data signal, said phase shifter comprising a plurality of delay circuits connected in a series; an exclusive OR responsive to the input data signal and the phase shifted signal from the phase shifter; a phase-locked loop comprising a ring oscillator for providing an output synchronized to an output of the exclusive OR, said ring oscillator comprising a plurality of delay circuits connected in a loop; and means for operating the delay circuits of said phase shifter in accordance with the delays of the delay circuits of said ring oscillator to provide a 90° phase shift at the frequency of said output of said ring oscillator.

Claim 19

The combination recited in claim 15 wherein said delay circuits of said phase shifter are replicas of said delay circuits of said ring oscillator.

Claim 20

The combination recited in claim 16 wherein said delay circuits of said phase shifter and said ring oscillator comprise differential inverters.

Claim 21

The combination recited in claim 17 further comprising means for operating said differential inverters of said phase shifter under the same operating conditions as said differential inverters of said ring oscillator.

Claim 22

The combination recited in claim 18 further comprising a phase detector responsive to said output of said exclusive OR and said output of said ring oscillator, and wherein said operating means comprises means responsive to said phase detector for generating bias voltage for said differential inverters of said phase shifter and said ring oscillator.

Claim 23

A clock and data recovery system for an incoming non-return-to-zero input data signal, comprising: a phase shifter comprising a plurality of differential inverters connected in series, said phase shifter being adapted to receive a non-return-to-zero input data signal at a first one of said differential inverters in said series and provide an output signal from a last differential inverter in said series wherein said output signal is shifted in phase from said data input signal; an exclusive OR responsive to the input data signal and the phase shifted signal from said phase shifter to provide a signal including a frequency component of an originating clock of said non-return-to-zero input data; a phase-locked loop comprising a current controlled oscillator and a phase detector responsive to said signal from said exclusive OR and an output from said current controlled oscillator, said current controlled oscillator comprising a ring oscillator of differential inverters and being responsive to said phase detector to cause said output of said current controlled oscillator to be driven into synchronism with said frequency component of said originating clock of said non-return-to-zero input data; said differential inverters of said phase shifter being replicas and being operated under the same operating and bias conditions as said differential inverters of said ring oscillator to produce a total delay equal to 90° at the output frequency of said ring oscillator; said ring oscillator comprising an even number of differential inverters with the outputs of a single differential inverter being reversed to the inputs of another differential inverter in the ring of differential inverters to provide oscillation with said even number of differential inverters; said output from said current controlled oscillator to said phase detector being connected to the outputs of a first differential inverter; said current controlled oscillator having a quadrature output connected to the differential outputs of a differential inverter spaced half the total number of differential inverters in said ring from said first differential inverters; and a decision circuit having a data input fed by said non-return-to-zero input data signal and clock input fed by said quadrature output from said current controlled oscillator to provide clean logical outputs of l's and 0's.

Claim 24

A clock and data recovery system for an incoming non-return-to-zero input data signal, comprising: a phase shifter comprising a plurality of differential inverters connected in series, said phase shifter being adapted to receive a non-return-to-zero input data signal at a first one of said differential inverters in said series and provide an output signal from a last differential inverter in said series wherein said output signal is shifted in phase from said data input signal; an exclusive OR responsive to the input data signal and the phase shifted signal from said phase shifter to provide a signal including a frequency component of an originating clock of said non-return-to-zero input data; a phase-locked loop comprising a current controlled oscillator and a phase detector responsive to said signal from said exclusive OR and an output from said current controlled oscillator, said current controlled oscillator comprising a ring oscillator of differential inverters and being responsive to said phase detector to cause said output of said current controlled oscillator to be driven into synchronism with said frequency component of said originating clock of said non-return-to-zero input data; said differential inverters of said phase shifter being replicas and being operated under the same operating and bias conditions as said differential inverters of said ring oscillator to produce a total delay equal to 90° at the output frequency of said ring oscillator; said ring oscillator comprising an even number of differential inverters with the outputs of a single differential inverter being reversed to the inputs of another differential inverter in the ring of differential inverters to provide oscillation with said even number of differential inverters; said output from said current controlled oscillator to said phase detector being connected to the outputs of a first differential inverter; said current controlled oscillator having a quadrature output connected to the differential outputs of a differential inverter spaced half the total number of differential inverters in said ring from said first differential inverters; and a decision circuit having a data input fed by said non-return-to-zero input data signal and clock input fed by said quadrature output from said current controlled oscillator to provide clean logical outputs of l's and 0's.

Claim 27

The method recited in claim 21 wherein said phase shifting step comprises a step of passing said non-return-to-zero input data signal through a series of differential inverters.

Claim 28

The method recited in claim 22 wherein said current controlled oscillator comprises a ring of differential inverters, and said delay controlling step comprises a step of operating said differential inverters of said phase shifting step under the same operating and bias conditions as said differential inverters of said current controlled oscillator to cause each of said differential inverters of said phase shifting step to have the same delay as said differential inverters of said current controlled oscillator.