US5163067A
Expired / Lapsed
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Method and apparatus for decoding Manchester encoded data
Assignee: Nortel Networks Ltd
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Filing: 1991-11-21
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Granted: 1992-11-10
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Expires: 2011-11-21
Abstract
Abstract A receiver for Manchester encoded data includes an autocalibration feedback loop that generates a timing pulse used to recover the clock and data signals. The autocalibration feedback loop includes a first digital delay line sampled by a plurality of D-type flip-flops in dependence upon the recovered clock signal to produce a control word CNT(O:N) indicative of the number of digital delay elements required to approximate one-half of the recovered clock period. A second digital delay line, connectivity mapped to the first, provides three-eights of a clock period delay. The delayed clock signal is derived from the bit stream by sampling in dependence upon the timing pulse. The decoded data signal is derived from the bit stream by multiplexing the sampling input in dependence upon the timing pulse and the decoded data signal.
Inventors
- 👤 Mark S. Wight
- 👤 Mervin Doda
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 07:33
CPC Classifications
H; H04; H04L; H04L25/00; H04L25/38; H04L25/40; H04L25/49; H04L25/4904; H04L7/00; H04L7/02; H04L7/033; H04L7/0337; H04L7/04; H04L7/041; H04L7/046
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
89 words
A method of decoding data represented by a bit stream in which 10 and 01 bit sequences represent data bits, comprising the steps of: producing a clock signal with a period corresponding to twice the duration of each data bit and having a falling edge delayed by a holding time from a falling edge of the bit stream; producing a timing pulse having a falling edge defined by the falling edge of the clock signal; and producing decoded data from the bit stream in dependence upon the timing pulse.
Claim 2
Independent Claim
89 words
A method of decoding data represented by a bit stream in which 10 and 01 bit sequences represent data bits, comprising the steps of: producing a clock signal with a period corresponding to twice the duration of each data bit and having a falling edge delayed by a holding time from a falling edge of the bit stream; producing a timing pulse having a falling edge defined by the falling edge of the clock signal; and producing decoded data from the bit stream in dependence upon the timing pulse.
Claim 3
Dependent Claim
75 words
A method as claimed in claim 1 wherein the step of producing a timing pulse includes the steps of determining a first number of digital delay elements required to approximate one-half of the clock signal period, a second number of digital delay elements, for delaying the clock signal an amount corresponding to about three quarters of the first number and exclusive NORing the clock signal with the delayed clock signal to produce the timing pulse.
Claim 4
Dependent Claim
93 words
Apparatus for decoding data represented by a bit stream in which 10 and 01 bit sequences represent data bits, comprising: first means for producing a clock signal with a period corresponding to twice the duration of each data bit and having a falling edge delayed by a holding time from a falling edge of the bit stream; second means for producing a timing pulse having a falling edge defined by the falling edge of the clock signal; and third means producing decoded data from the bit stream in dependence upon the timing pulse.
Claim 5
Dependent Claim
93 words
Apparatus for decoding data represented by a bit stream in which 10 and 01 bit sequences represent data bits, comprising: first means for producing a clock signal with a period corresponding to twice the duration of each data bit and having a falling edge delayed by a holding time from a falling edge of the bit stream; second means for producing a timing pulse having a falling edge defined by the falling edge of the clock signal; and third means producing decoded data from the bit stream in dependence upon the timing pulse.
Claim 6
Dependent Claim
80 words
Apparatus as claimed in claim 3 wherein the second means includes first digital delay means for determining a first number of digital delay elements required to approximate one-half of the clock signal period, second digital delay means for providing, a second number of digital delay elements, for delaying the clock signal an amount corresponding to about three quarters of the first number and means for exclusive NORing the clock signal with the delayed clock signal to produce the timing pulse.
Claim 7
Dependent Claim
57 words
Apparatus as claimed in claim 4 wherein first digital delay means includes a plurality of series connected digital delay elements for providing a plurality of delayed clock signals and a plurality of D-type flip flops for sampling the plurality of delayed clock signals to produce a control word indicative of the second number of digital delay elements.
Claim 8
Dependent Claim
31 words
Apparatus as claimed in claim 5 wherein second digital delay means includes a plurality of series connected digital delay multiplexers for delaying the clock signal in dependence upon the control word.
Claim 9
Dependent Claim
34 words
Apparatus as claimed in claim 6 wherein second digital delay means includes connectivity means for mapping the control word to a set of control bits for selecting signals input to the digital delay mutliplexers.
Claim 10
Dependent Claim
41 words
Apparatus as claimed in claim 7 wherein connectivity means maps control signals CTL(1), CTL(2), . . . , CTL(n) to select signals CTL(2), . . . XTL(k) in accordance with the following: XTL(i)←CTL(j) where j=i*4/3 rounded off to a positive integer.
Claim 11
Dependent Claim
28 words
Apparatus as claimed in claim 8 wherein the digital delay multiplexers include redundant decoding for preventing a metastable signal at an input from being propagated to an output.
Claim 12
Dependent Claim
35 words
Apparatus as claimed in claim 9 wherein the digital delay output is given by: output=i0*i1+sel*i0+sel*i1, where, i0 and i1 are the input signals to the multiplexer, and sel is the select input to the multiplexer.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-11-10 | 1996-05-11 | 1996-11-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-11-10 | 2000-05-11 | 2000-11-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-11-10 | 2004-05-11 | 2004-11-10 | $7700.00 | Window Closed / Lapsed |