Phase detector for phase locked loops

Claim 2

A phase processing system comprising: logic level pulse means for converting a sinusoidal signal input to logic level signal, a counting means, an adder means, driving means responsive to said logic level pulse means for driving said counting means, said counting means driving said adder means whereby the outputs of said counting means are added in said adder means with the carry signal ignored, the most significant bit from said adder means being 0 when said adding means is less than half its range and being 1 when the output of said adder means is above-mid-range, and decoding means for decoding the output of said adder means to block upcount when the adder output exceeds a first predetermined limit and to block downcount when the adder output falls below a second predetermined limit.

Claim 3

The phase processing system of claim 1 wherein said means for converting said sinusoidal signal input to logic level signals comprises a comparator.

Claim 4

The phase processing system of claim 2 wherein said driving means produces short positive pulses and comprises an edge detector consisting of a flip-flop circuit and an exclusive OR gate, said edge detector providing a linear range of π radians for said phase processing system.

Claim 5

The phase processing system of claim 3 wherein said means for driving said counting means comprises NAND gates having inputs from said edge detector to drive an up counting means and a down counting means.

Claim 6

A phase processing system comprising: a comparator for converting a sinusoidal signal input to a logic level signal, a voltage controlled oscillator, a first edge detector connected to the output of said comparator, a second edge detector connected to the output of said voltage controlled oscillator, said first and second edge detectors each comprising an exclusive OR gate and a flip-flop circuit, and producing a short positive pulse when said logic level signal and said voltage controlled oscillator change state, a first NAND gate connected to the output of said first edge detector, a second NAND gate connected to the output of said second edge detector, an up counter connected to the output of said first NAND gate, a down counter connected to the output of said second NAND gate, an adder circuit, said up counter and said down counter connected to said adder circuit whereby the outputs of said counters are added in said adder circuit and the most significant bit from said adder circuit being zero when said adder circuit output is less than half its range and being one when the output of said adder circuit is above mid-range, and a decoder circuit connected to the output of said adder circuit to block upcount when adder output exceeds a first predetermined limit and to block downcount when adder output falls below a second predetermined limit.

Claim 7

A phase processing system comprising: a comparator for converting a sinusoidal signal input to a logic level signal, a voltage controlled oscillator, a first edge detector connected to the output of said comparator, a second edge detector connected to the output of said voltage controlled oscillator, said first and second edge detectors each comprising an exclusive OR gate and a flip-flop circuit, and producing a short positive pulse when said logic level signal and said voltage controlled oscillator change state, a first NAND gate connected to the output of said first edge detector, a second NAND gate connected to the output of said second edge detector, an up counter connected to the output of said first NAND gate, a down counter connected to the output of said second NAND gate, an adder circuit, said up counter and said down counter connected to said adder circuit whereby the outputs of said counters are added in said adder circuit and the most significant bit from said adder circuit being zero when said adder circuit output is less than half its range and being one when the output of said adder circuit is above mid-range, and a decoder circuit connected to the output of said adder circuit to block upcount when adder output exceeds a first predetermined limit and to block downcount when adder output falls below a second predetermined limit.

Claim 8

A phase processing system comprising: a source of logic level signal inputs, means responsive to said logic level signal inputs for producing positive pulses as said logic level signals change their state, a first counting means for separating time periods, a second counting means controlled by said first counting means and connected to said means for producing positive pulses for counting up said pulses during an up counting period and for counting down during a down counting period, and decoding means for decoding the output of said second counting means to block upcount when the second counter output exceeds a first predetermined limit and to block downcount when the second counter output falls below a second predetermined limit.

Claim 9

A phase processing system comprising: a source of logic level signal inputs, means responsive to said logic level signal inputs for producing positive pulses as said logic level signals change their state, a first counting means for separating time periods, a second counting means controlled by said first counting means and connected to said means for producing positive pulses for counting up said pulses during an up counting period and for counting down during a down counting period, and decoding means for decoding the output of said second counting means to block upcount when the second counter output exceeds a first predetermined limit and to block downcount when the second counter output falls below a second predetermined limit.

Claim 10

The phase processing system of claim 6 comprising: means for converting sinusoidal signals into said logic level signals.

Claim 11

The phase processing system of claim 7 wherein said means responsive to said logic level inputs comprises an edge detector comprising an exclusive OR gate, a NAND gate and a flip flop circuit.

Claim 12

The phase processing system of claim 8 comprising NAND gates connected to said edge detector and said decoding means for driving said counting means.

Claim 13

A phase processing system comprising: a comparator for converting a sinusoidal signal input into a logic level signal, a voltage controlled oscillator, a first edge detector connected to the output of said comparator, a second edge detector connected to the output of said voltage controlled oscillator, an up/down counter connected to said first and second edge detectors, and a decoder connected to said up/down counter whereby the phase error output signal of said phase processing system is made to rapidly follow the phase difference of the input signals.

Claim 14

A phase processing system comprising: a comparator for converting a sinusoidal signal input into a logic level signal, a voltage controlled oscillator, a first edge detector connected to the output of said comparator, a second edge detector connected to the output of said voltage controlled oscillator, an up/down counter connected to said first and second edge detectors, and a decoder connected to said up/down counter whereby the phase error output signal of said phase processing system is made to rapidly follow the phase difference of the input signals.

Claim 15

A phase processing system comprising: means for converting a sinusoidal signal input to logic level signal, a counting means, an adder means, said counting means driving said adder means whereby the outputs of said counting means are added in said adder means with the carry signal ignored, the most significant bit from said adder means being 0 when said adding means is less than half its range and being 1 when the output of said adder means is above mid-range, and decoding means for decoding the output of said adder means to block upcount when the adder output exceeds a first predetermined limit and to block downcount when the adder output falls below a second predetermined value.

Claim 16

A phase processing system comprising: means for converting a sinusoidal signal input to logic level signal, a counting means, an adder means, said counting means driving said adder means whereby the outputs of said counting means are added in said adder means with the carry signal ignored, the most significant bit from said adder means being 0 when said adding means is less than half its range and being 1 when the output of said adder means is above mid-range, and decoding means for decoding the output of said adder means to block upcount when the adder output exceeds a first predetermined limit and to block downcount when the adder output falls below a second predetermined value.