US3723889A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Phase and frequency comparator
Assignee: AT&T Inc
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Filing: 1971-12-22
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Granted: 1973-03-27
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Expires: 1991-12-22
Abstract
Abstract A sawtooth phase comparator is arranged to act as a frequency comparator when the frequencies of the input and reference signals differ by a substantial amount. This is accomplished by using a phase comparator consisting of a flip-flop with first and second frequency counters connected between the input signal and its SET input, and between the reference signal and its RESET input, respectively. Means are provided for inhibiting the input signal whenever it would cause a signal to appear at the set input of the flip-flop when it is already set and for inhibiting the reference signal whenever it would cause a signal to appear at the RESET input when it is already reset. This eliminates the alternating polarity signal which prior art comparators produce when the linear portion of the transfer characteristic is exceeded. Consequently, a frequency correcting signal is produced.
Inventors
- 👤 J Oberst
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 10:57
CPC Classifications
H; H03; H03D; H03D13/00; H03D13/003; G; G01; G01R; G01R23/00
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
139 words
A phase and frequency comparator which compares the phase and frequency of an input signal with that of a reference signal and produces an output signal related to the difference in phase and frequency, comprising: means for inhibiting the input and reference signals in response to first and second inhibit signals; means for separately counting the pulses of the input and reference signals which pass through said means for inhibiting and for producing output levels for every Nth pulse; switching means, responsive to the outputs of said means for inhibiting and said means for separately counting, for producing first and second complementary digital signals, the first complementary signal being the output of said comparator; and means for generating the first and second inhibit signals in response to the output of saiD means for separately counting, and said switching means.
Claim 2
Dependent Claim
139 words
A phase and frequency comparator which compares the phase and frequency of an input signal with that of a reference signal and produces an output signal related to the difference in phase and frequency, comprising: means for inhibiting the input and reference signals in response to first and second inhibit signals; means for separately counting the pulses of the input and reference signals which pass through said means for inhibiting and for producing output levels for every Nth pulse; switching means, responsive to the outputs of said means for inhibiting and said means for separately counting, for producing first and second complementary digital signals, the first complementary signal being the output of said comparator; and means for generating the first and second inhibit signals in response to the output of saiD means for separately counting, and said switching means.
Claim 3
Dependent Claim
79 words
A comparator as claimed in claim 1 wherein said means for inhibiting comprises: a first INHIBIT gate with the input signal applied to the normal input and the first inhibit signal applied to the inhibit input; and a second INHIBIT gate with the reference signal applied to the normal input and the second inhibit signal applied to the inhibit input, the outputs of said first and second INHIBIT gates being said pulses which pass through said means for inhibiting.
Claim 4
Dependent Claim
51 words
A comparator as claimed in claim 2 wherein said means for separately counting comprises: a first counter circuit for producing an output level for every Nth pulse from said first INHIBIT gate; and a second counter circuit for producing an output level for every Nth pulse from said second INHIBIT gate.
Claim 5
Dependent Claim
155 words
A comparator as claimed in claim 3 wherein said switching means comprises: a first AND gate for combining the outputs of said first counter circuit and said first INHIBIT gate; a second AND gate for combining the outputs of said second counter circuit and said second INHIBIT gate; and a reset-set flip-flop having complementary Q and Q outputs, the Q output being at a high digital level when the SET input is activated and the Q output being at a high digital level when the RESET input is activated, the output of said first AND gate being applied to the SET input of said flip-flop, the output of said second AND gate applied to the RESET input of said flip-flop, the output of the comparator and the first complementary signal being the signal at the Q output of said flip-flop and the second complementary signal being the signal at the Q output of said flip-flop.
Claim 6
Dependent Claim
85 words
A comparator as claimed in claim 4 wherein said means for generating the first and second inhibit signals comprises: a third AND gate for combining the Q output of said flip-flop and the output of said first counter circuit, and a fourth AND gate for combining the Q output of said flip-flop and the output of said second counter circuit, the output of said third AND gate being the first inhibit signal and the output of said fourth AND gate being the second inhibit signal.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-03-26 | 1976-09-25 | 1977-03-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-03-26 | 1980-09-25 | 1981-03-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-03-26 | 1984-09-25 | 1985-03-27 | $7700.00 | Window Closed / Lapsed |