US5142247A
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US
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Multiple frequency phase-locked loop clock generator with stable transitions between frequencies
Assignee: Hewlett Packard Development Co LP
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Filing: 1991-08-06
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Granted: 1992-08-25
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Expires: 2011-08-06
Abstract
Abstract A phase-locked loop (PLL) clock generator circuit which is capable of changing the frequency of its outpt clock signal in a stable fashion. Selection of the frequency of the output clock signal is made by way of a selectable frequency divider coupled between the reference clock signal and an input of the PLL, with another frequency divider in the feedback loop of the PLL; each of these frequency dividers are selectable according to a signal on a select bus, translated by way of a ROM look-up table. The circuit also includes a multiplexer having a first input coupled to the PLL output, and a second input coupled to a stable clock signal, for example to the referenc clock signal or to the output of a fixed frequency PLL. The conrol input of the multiplexer is controlled by a state machine which monitors the select bus. Responsive to detection of a transition of the select bus, indicating a new frequency, the state machine issues a pulse to the control input of the multiplexer to cause it to select the stable clock signal for sufficient time to allow the PLL to acquire and lock onto the new frequency, after which the multiplexer again selects the PLL output as the output clock signal. As a result, the unstable and non-linear behavior at the PLL output does not appear at the output of the circuit, with a stable clock signal at a safe frequency appearing thereat during the PLL transitional cycles.
Inventors
- 👤 Henry F. Lada, Jr.
- 👤 Hung Q. Le
- 👤 James H. Garrett
- 👤 John M. Gromala
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 21:22
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/16; H03L7/18
Claims Analysis
Total Claims: 32
Claim 1
Independent Claim
132 words
A clock generator circuit, comprising: a phase-locked loop, coupled to receive a reference clock signal; means, coupled to an input of said phase-locked loop and to a select input, for selecting a frequency multiple of said reference clock signal to be generated by said phase-locked loop; a multiplexer, having a first input coupled to the output of said phase-locked loop, having a second input for receiving a stable clock signal, having an output, and having a control input for selecting said first or second input to be coupled to said output; and means, coupled to said select input of said selecting means, and to said control input of said multiplexer, for controlling said multiplexer to select said stable clock signal for a duration of time following a transition at said select input.
Claim 2
Dependent Claim
132 words
A clock generator circuit, comprising: a phase-locked loop, coupled to receive a reference clock signal; means, coupled to an input of said phase-locked loop and to a select input, for selecting a frequency multiple of said reference clock signal to be generated by said phase-locked loop; a multiplexer, having a first input coupled to the output of said phase-locked loop, having a second input for receiving a stable clock signal, having an output, and having a control input for selecting said first or second input to be coupled to said output; and means, coupled to said select input of said selecting means, and to said control input of said multiplexer, for controlling said multiplexer to select said stable clock signal for a duration of time following a transition at said select input.
Claim 3
Dependent Claim
46 words
The circuit of claim 1, wherein said selecting means comprises: a first frequency divider, having an input coupled to receive said reference clock signal, having a control input coupled to said select input, and having an output coupled to a first input of said phase-locked loop.
Claim 4
Dependent Claim
48 words
The circuit of claim 2, wherein said selecting means further comprises: a second frequency divider, having an input coupled to the output of said phase-locked loop, having a control input coupled to said select input, and having an output coupled to a feedback input of said phase-locked loop.
Claim 5
Dependent Claim
60 words
The circuit of claim 3, wherein said selecting means further comprises: a memory, having an address input coupled to said select input, and having an output coupled to said control input of said first and second frequency dividers, for translating the value of the signal at said select input into a control signal for said first and second frequency dividers.
Claim 6
Dependent Claim
46 words
The circuit of claim 1, wherein said selecting means comprises: a frequency divider, having an input coupled to the output of said phase-locked loop, having a control input coupled to said select input, and having an output coupled to a feedback input of said phase-locked loop.
Claim 7
Dependent Claim
12 words
The circuit of claim 1, wherein said controlling means comprises sequential logic.
Claim 8
Dependent Claim
35 words
The circuit of claim 1, wherein said controlling means comprises: means for detecting a transition of said select input; and means, responsive to said detecting means, for generating a pulse for application to said multiplexer.
Claim 9
Dependent Claim
12 words
The circuit of claim 7, wherein said generating means comprises: a timer.
Claim 10
Dependent Claim
43 words
The circuit of claim 8, wherein said timer comprises: a counter for counting reference clock cycles; and a comparator, for comparing the output of said counter to a time value, and for ending said pulse responsive to said counter equaling said time value.
Claim 11
Dependent Claim
12 words
The circuit of claim 8, wherein said timer comprises: an RC network.
Claim 12
Dependent Claim
35 words
The circuit of claim 7, wherein said generating means comprises means for monitoring said phase-locked loop so that said pulse is presented to said multiplexer during transitional cycles at the output of said phase-locked loop.
Claim 13
Dependent Claim
114 words
A circuit for generating a clock signal, comprising: a phase-locked loop having a first input coupled to receive a reference clock signal; a first frequency divider, coupled to an input of said phase-locked loop, and coupled to a select input, for selecting a frequency multiple of said reference clock signal to be generated by said phase-locked loop; an output control circuit, coupled to receive the output of said phase-locked loop and a stable clock signal, having an output corresponding to the output of the circuit, for monitoring said select input for transitions thereat, and for applying said stable clock signal at its output for a selected duration following a transition at said select input.
Claim 14
Dependent Claim
114 words
A circuit for generating a clock signal, comprising: a phase-locked loop having a first input coupled to receive a reference clock signal; a first frequency divider, coupled to an input of said phase-locked loop, and coupled to a select input, for selecting a frequency multiple of said reference clock signal to be generated by said phase-locked loop; an output control circuit, coupled to receive the output of said phase-locked loop and a stable clock signal, having an output corresponding to the output of the circuit, for monitoring said select input for transitions thereat, and for applying said stable clock signal at its output for a selected duration following a transition at said select input.
Claim 15
Dependent Claim
104 words
The circuit of claim 12, wherein said output control circuit comprises: logic circuitry having an input coupled to said select input, and having an output, for monitoring transitions of said select input and for generating a pulse at its output responsive thereto; and a multiplexer, having a first input coupled to the output of said phase-locked loop, having a second input coupled to said stable clock signal, having a control input coupled to the output of said logic circuitry, and having an output for presenting said output of said phase-locked loop or said stable clock signal responsive to signals received at its control input.
Claim 16
Dependent Claim
56 words
The circuit of claim 12, wherein said output of said first frequency divider is coupled to a first input of said phase-locked loop; wherein of said first frequency divider has an input coupled to receive said reference clock signal; and wherein said phase-locked loop has a feedback input coupled to the output of said phase-locked loop.
Claim 17
Dependent Claim
71 words
The circuit of claim 14, further comprising: a second frequency divider, having an input coupled to the output of said phase-locked loop, having an output coupled to said feedback input of said phase-locked loop, and coupled to said select input; wherein the ratio of the multiples of said second and first frequency dividers corresponds to the selected frequency multiple of said reference clock signal to be generated by said phase-locked loop.
Claim 18
Dependent Claim
56 words
The circuit of claim 12, wherein said output of said first frequency divider is coupled to a feedback input of said phase-locked loop; wherein said first frequency divider has an input coupled to the output of said phase-locked loop; and wherein a first input of said phase-locked loop is coupled to receive said reference clock signal.
Claim 19
Independent Claim
137 words
A method of operating a phase-locked loop-based clock generator circuit to change the frequency of the signal at its output responsive to a transition of a select signal applied to said circuit, said circuit including a phase-locked loop, said method comprising: detecting the transition of said select signal indicating a new frequency of operation for said circuit; responsive to said detecting step, decoupling the output of said phase-locked loop from the output of said clock generator circuit for a period of time; coupling a stable clock signal to the output of said clock generator circuit for said period of time; and after said period of time has elapsed, coupling the output of said phase-locked loop to the output of said clock generator circuit and decoupling said stable clock signal from the output of said clock generator circuit.
Claim 20
Independent Claim
137 words
A method of operating a phase-locked loop-based clock generator circuit to change the frequency of the signal at its output responsive to a transition of a select signal applied to said circuit, said circuit including a phase-locked loop, said method comprising: detecting the transition of said select signal indicating a new frequency of operation for said circuit; responsive to said detecting step, decoupling the output of said phase-locked loop from the output of said clock generator circuit for a period of time; coupling a stable clock signal to the output of said clock generator circuit for said period of time; and after said period of time has elapsed, coupling the output of said phase-locked loop to the output of said clock generator circuit and decoupling said stable clock signal from the output of said clock generator circuit.
Claim 21
Dependent Claim
48 words
The method of claim 17, wherein said coupling and decoupling steps are each performed by controlling a multiplexer, said multiplexer having inputs for receiving the output of said phase-locked loop and said stable clock signal, and having an output coupled to the output of said clock generator circuit.
Claim 22
Dependent Claim
15 words
The method of claim 18, wherein said period of time is determined by a timer.
Claim 23
Dependent Claim
32 words
The method of claim 17, wherein an input of said phase-locked loop is coupled to a reference clock signal; and wherein said stable clock signal is generated from said reference clock signal.
Claim 24
Dependent Claim
55 words
The method of claim 20, wherein said reference clock signal is coupled to the input of said phase-locked loop by way of a frequency divider adapted to divide the reference clock signal by a selected multiple; and further comprising: selecting the multiple of said frequency divider according to the value of s id select signal.
Claim 25
Independent Claim
170 words
A method of controlling the operation of a clock generator circuit including a phase-locked loop, for generating an output clock signal having a frequency selectable by way of a select signal, comprising the steps of: coupling the output of said phase-locked loop to a first input of a multiplexer, said multiplexer having first and second inputs and a control input, said multiplexer having an output for presenting the output clock signal; coupling a stable clock signal to the second input of said multiplexer; detecting a transition of said select signal which indicates selection of a different frequency for said output clock signal; responsive to said detecting step, applying a first signal to the control input of said multiplexer so that said multiplexer selects said stable clock signal for connection to its output; after a duration of time has elapsed after said applying step, applying a second signal to the control input of said multiplexer so that said multiplexer selects the output of said phase-locked loop for connection to its output.
Claim 26
Independent Claim
170 words
A method of controlling the operation of a clock generator circuit including a phase-locked loop, for generating an output clock signal having a frequency selectable by way of a select signal, comprising the steps of: coupling the output of said phase-locked loop to a first input of a multiplexer, said multiplexer having first and second inputs and a control input, said multiplexer having an output for presenting the output clock signal; coupling a stable clock signal to the second input of said multiplexer; detecting a transition of said select signal which indicates selection of a different frequency for said output clock signal; responsive to said detecting step, applying a first signal to the control input of said multiplexer so that said multiplexer selects said stable clock signal for connection to its output; after a duration of time has elapsed after said applying step, applying a second signal to the control input of said multiplexer so that said multiplexer selects the output of said phase-locked loop for connection to its output.
Claim 27
Dependent Claim
19 words
The method of claim 22, further comprising: measuring said duration of time after said applying step with a timer.
Claim 28
Dependent Claim
11 words
The method of claim 23, wherein said timer comprises a counter.
Claim 29
Dependent Claim
32 words
The method of claim 22, wherein a reference clock signal is coupled to an input of said phase-locked loop; and wherein said stable clock signal is generated from said reference clock signal.
Claim 30
Dependent Claim
66 words
The method of claim 22, wherein a reference clock signal is coupled to an input of said phase-locked loop by way of a frequency divider, said frequency divider adapted to divide the reference clock signal by a selected multiple for application to the input of said phase-locked loop; and further comprising: selecting the multiple of said frequency divider according to the value of said select signal.
Claim 31
Dependent Claim
21 words
The method of claim 22, further comprising: determining said duration of time from the frequency acquisition time of said phase-locked loop.
Claim 32
Dependent Claim
14 words
The method of claim 27, wherein said determining step comprises monitoring said phase-locked loop.
References Cited (Backward Citations)
US3899746A
Cited
US5036216A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-08-25 | 1996-02-24 | 1996-08-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-08-25 | 2000-02-24 | 2000-08-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-08-25 | 2004-02-24 | 2004-08-25 | $7700.00 | Window Closed / Lapsed |