US5029282A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Voltage regulator circuit
Assignee: Toshiba Corp
•
Filing: 1989-12-14
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Granted: 1991-07-02
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Expires: 2009-12-14
Abstract
Abstract A voltage regulator circuit for use with an integrated circuit with a charge pump circuit having a voltage output terminal and a voltage input terminal in which a plurality of voltage regulating P-channel MOS transistors, each of which has its source and substrate connected together and its gate and drain connected together, are connected in series between the voltage output and input terminals of the charge pump circuit.
Inventors
- 👤 Makoto Ito
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 13:24
CPC Classifications
G; G05; G05F; G05F3/00; G05F3/02; G05F3/08; G05F3/10; G05F3/16; G05F3/20; G05F3/205; G11; G11C; G11C5/00; G11C5/14; G11C5/147; G05F3/24; G11C16/00; G11C16/02; G11C16/06; G11C16/30; G11C5/145; H; H02; H02M; H02M3/00; H02M3/02; H02M3/04; H02M3/06; H02M3/07; H02M3/073; H10; H10D; H10D89/00; H10D89/60; H10D89/601; H10D89/811; H10D89/819
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
71 words
A voltage regulator circuit for use with a semiconductor integrated circuit having a charge pump circuit with a voltage output terminal and a voltage input terminal, including a plurality of P-channel MOS transistors connected in series between said voltage output terminal and said voltage input terminal of said charge pump circuit, each of said P-channel MOS transistors having its source and substrate connected together and its gate and drain connected together.
Claim 2
Dependent Claim
71 words
A voltage regulator circuit for use with a semiconductor integrated circuit having a charge pump circuit with a voltage output terminal and a voltage input terminal, including a plurality of P-channel MOS transistors connected in series between said voltage output terminal and said voltage input terminal of said charge pump circuit, each of said P-channel MOS transistors having its source and substrate connected together and its gate and drain connected together.
Claim 3
Dependent Claim
66 words
A voltage regulator circuit according to claim 1, in which between one end of the series connection of said P-channel MOS transistors and said voltage output terminal of said charge pump circuit is connected a P-channel MOS transistor which has its source and substrate connected together and is supplied at its gate with an enable signal synchronized with an enable signal for said charge pump circuit.
Claim 4
Dependent Claim
50 words
A voltage regulator circuit according to claim 1, in which between the other end of the series connection of said P-channel MOS transistors and said voltage input terminal of said charge pump circuit is connected a P-channel MOS transistor having its substrate, gate and drain connected together or a diode.
Claim 5
Dependent Claim
50 words
A voltage regulator circuit according to claim 2, in which a P-channel MOS transistor having its substrate, gate and drain connected together or a diode is connected between the other end of the series connection of said P-channel MOS transistors and said voltage input terminal of said charge pump circuit.
Claim 6
Dependent Claim
30 words
A voltage regulator circuit according to claim 1, in which said voltage regulator circuit regulates a boosted voltage to be applied to memory cells of a nonvolatile memory integrated circuit.
Claim 7
Dependent Claim
30 words
A voltage regulator circuit according to claim 2, in which said voltage regulator circuit regulates a boosted voltage to be applied to memory cells of a nonvolatile memory integrated circuit.
Claim 8
Dependent Claim
30 words
A voltage regulator circuit according to claim 3, in which said voltage regulator circuit regulates a boosted voltage to be applied to memory cells of a nonvolatile memory integrated circuit.
Claim 9
Dependent Claim
30 words
A voltage regulator circuit according to claim 4, in which said voltage regulator circuit regulates a boosted voltage to be applied to memory cells of a nonvolatile memory integrated circuit.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-07-01 | 1994-12-31 | 1995-07-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-07-01 | 1998-12-31 | 1999-07-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-07-01 | 2002-12-31 | 2003-07-02 | $7700.00 | Window Closed / Lapsed |