A MIS device including a substrate bias generating circuit

Claim 2

An MIS device including a substrate bias generating circuit for absorbing charges in a semiconductor substrate of the device, characterised by a bias circuit (3) connected to the semiconductor substrate to perform charging and discharging operations upon the semiconductor substrate in accordance with clock signals (Q, so as to absorb the charges in the semiconductor substrate; and a clamp circuit (4) connected between the semiconductor substrate and a predetermined reference power supply.

Claim 3

An MIS device including a substrate bias generating circuit for absorbing charges in a semiconductor substrate of the device, characterised by first and second power supply lines (V DD , V SS ); an oscillating circuit (1) for generating clock signals (Q, Q ); a charging and discharging circuit (2) connected to the first and second power supply lines and to the oscillating circuit to generate an output signal which has a potential equal to the potential of the first or second power supply lines in response to the clock signals; a bias circuit (3) connected to the charging and discharging circuit (2), to the semiconductor substrate and to the second power supply line (V SS ) for absorbing the charges in the semiconductor substrate in response to the output signal of the charging and discharging circuit; and a clamp circuit (4) connected to the semiconductor substrate and the second power supply line (V SS ) to clamp the potential of the semiconductor substrate.

Claim 4

An MIS device including a substrate bias generating circuit for absorbing charges in a semiconductor substrate of the device, characterised by first and second power supply lines (V DD , V SS ); an oscillating circuit (1) for generating clock signals (Q, Q ); a charging and discharging circuit (2) connected to the first and second power supply lines and to the oscillating circuit to generate an output signal which has a potential equal to the potential of the first or second power supply lines in response to the clock signals; a bias circuit (3) connected to the charging and discharging circuit (2), to the semiconductor substrate and to the second power supply line (V SS ) for absorbing the charges in the semiconductor substrate in response to the output signal of the charging and discharging circuit; and a clamp circuit (4) connected to the semiconductor substrate and the second power supply line (V SS ) to clamp the potential of the semiconductor substrate.

Claim 5

A device as claimed in Claim 2, characterised in that the two clock signals (Q, Q ) are in phase opposition.

Claim 6

A device as claimed in Claim 2 or Claim 3, characterised in that the charging and discharging circuit (2) comprises first and second transistors (T 1 , T 2 ) connected in series between the first and second power supply lines (V DD , V SS ), the gates of the first and second transistors receiving the clock signals (Q, Q), and a first node (A) between the first and second transistors serving as an output of the charging and discharging circuit.

Claim 7

A device as claimed in Claim 2, Claim 3 or Claim 4, characterised in that the bias circuit (3) comprises a capacitor (C ) connected to the charging and discharging circuit (2); and third and fourth transistors (T 3 , T 4 ) which are diode-connected and are connected in series between the substrate and the second power supply line (V SS ), a second node (B) between the third and fourth transistors being connected to the capacitor.

Claim 10

A device as claimed in Claim 7, characterised in that a plurality of contact throughholes (C) is provided between the conductive layer (53) and the substrate.