US4439692A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Feedback-controlled substrate bias generator
Assignee: Signetics Corp
•
Filing: 1981-12-07
•
Granted: 1984-03-27
•
Expires: 2001-12-07
Abstract
Abstract A semiconductor circuit supplies a substrate back bias voltage that is feedback controlled as a function of the sum of the positive threshold voltage of one field-effect transistor (FET) and the negative threshold voltage of a second FET. Preferably, one of the FET's is an enhancement-mode device, and the other is a like-polarity depletion-mode device. This arrangement enables the bias voltage to vary from chip to chip in such a manner as to speed up the logic gates on a chip containing the slowest gates and to slow down the logic gates on a chip containing the fastest logic gates, thereby decreasing the chip-to-chip spread in gate propagation delay and average power dissipation. The worst-case noise margin increases slightly.
Inventors
- 👤 Jan J. P. M. Beekmans
- 👤 John B. Hughes
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 18:15
CPC Classifications
G; G05; G05F; G05F3/00; G05F3/02; G05F3/08; G05F3/10; G05F3/16; G05F3/20; G05F3/205
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
182 words
A circuit for generating a bias voltage for a semiconductor substrate wherein the circuit has oscillating means for repetitively supplying an oscillating signal at a given frequency, gating means responsive to the oscillating signal and to a feedback signal for supplying a gating signal which varies at the given frequency only when the feedback signal achieves a specified first relationship, pumping means responsive to the gating signal for supplying the bias voltage on an output line and for causing the bias voltage to move unidirectionally toward a desired value only when the gating signal achieves a specified second relationship, and feedback means responsive to the bias voltage for providing the feedback signal, characterized in that the feedback means comprises a field-effect transistor (FET) having a positive threshold voltage and an FET having a negative threshold voltage so arranged that the feedback signal achieves the first relationship when the absolute value of a reference voltage comprising the sum of the threshold voltages is at least equal to the absolute value of an internal voltage bearing a specified third relationship to the bias voltage.
Claim 2
Dependent Claim
182 words
A circuit for generating a bias voltage for a semiconductor substrate wherein the circuit has oscillating means for repetitively supplying an oscillating signal at a given frequency, gating means responsive to the oscillating signal and to a feedback signal for supplying a gating signal which varies at the given frequency only when the feedback signal achieves a specified first relationship, pumping means responsive to the gating signal for supplying the bias voltage on an output line and for causing the bias voltage to move unidirectionally toward a desired value only when the gating signal achieves a specified second relationship, and feedback means responsive to the bias voltage for providing the feedback signal, characterized in that the feedback means comprises a field-effect transistor (FET) having a positive threshold voltage and an FET having a negative threshold voltage so arranged that the feedback signal achieves the first relationship when the absolute value of a reference voltage comprising the sum of the threshold voltages is at least equal to the absolute value of an internal voltage bearing a specified third relationship to the bias voltage.
Claim 3
Dependent Claim
112 words
A circuit as in claim 1 characterized in that a first of the FET's has a first source/drain element coupled to a supply of a substantially constant voltage and a gate electrode and a second source/drain element connected to each other, that the second of the FET's has a first source/drain element coupled to the gate electrode of the first FET, a gate electrode for receiving the internal voltage on an internal line, and a second source/drain element for supplying the feedback signal on a feedback line, and that the absolute value of the threshold voltage of the second FET exceeds the absolute value of the threshold voltage of the first FET.
Claim 4
Dependent Claim
33 words
A circuit as in claim 2 characterized in that the first FET is an enhancement-mode FET of a given polarity and that the second FET is a depletion-mode FET of the given polarity.
Claim 5
Dependent Claim
44 words
A circuit as in claim 3 characterized in that the absolute value of the reference voltage is (1) a maximum in the Fast Fast corner of the FET processing range and (2) a minimum in the Slow Slow corner of the FET processing range.
Claim 6
Dependent Claim
58 words
A circuit as in claim 4 characterized in that the absolute value of the difference between the constant voltage and the bias voltage when it reaches a substantially steady-state value is (1) a maximum in the Fast Fast corner of the FET processing range and (2) a minimum in the Slow Slow corner of the FET processing range.
Claim 7
Dependent Claim
98 words
A circuit as in claim 3 characterized in that introduction of a first semiconductor dopant at a nominal first dosage into the channel of the enhancement-mode FET sets its threshold voltage at a level different from its otherwise original level, that introduction of both the first dopant at the nominal first dosage and a second semiconductor dopant at a nominal second dosage into the channel of the depletion-mode FET sets its threshold voltage, and that the dopants are of opposite conductivity types with the second dopant being of the same conductivity type as any of the source/drain elements.
Claim 8
Dependent Claim
15 words
A circuit as in claim 6 characterized in that each introduction is an ion implantation.
Claim 9
Dependent Claim
91 words
A circuit as in claim 7 characterized in that absolute value of the threshold voltage of the enhancement-mode FET varies over its processing range from a minimum at the Fast Fast and Fast Slow corners to a maximum at the Slow Fast and Slow Slow corners and that the absolute value of the threshold voltage of the depletion-mode FET varies over its processing range from a minimum at the Slow Slow corner to a maximum at the Fast Fast corner and is intermediate at the Fast Slow and Slow Fast corners.
Claim 10
Dependent Claim
58 words
A circuit as in claim 8 characterized in that the absolute value of the difference between the constant voltage and the bias voltage when it reaches a substantially steady-state value varies from a minimum at the Slow Slow corner to a maximum at the Fast Fast corner and is intermediate at the Fast Slow and Slow Fast corners.
Claim 11
Dependent Claim
25 words
A circuit as in claim 4 characterized by an impedance element coupled between a voltage/current supply and the second source/drain element of the depletion-mode FET.
Claim 12
Dependent Claim
30 words
A circuit as in claim 4 characterized in that a resistive voltage divider divides the bias voltage to generate the internal voltage as a given fraction of the bias voltage.
Claim 13
Dependent Claim
25 words
A circuit as in claim 11 characterized in that the voltage divider comprises a pair of divider sections, each comprising at least one resistively-connected FET.
Claim 14
Dependent Claim
21 words
A circuit as in claim 11 characterized in that the voltage divider comprises a pair of resistors of polycrystalline semiconductor material.
Claim 15
Dependent Claim
21 words
A circuit as in claim 11 characterized by clamping means for preventing the bias voltage from entering a restricted voltage range.
Claim 16
Dependent Claim
20 words
A circuit as in claim 12 characterized in that the clamping means is coupled between the output and feedback lines.
Claim 17
Dependent Claim
52 words
A circuit as in claim 15 characterized in that the clamping means comprises a depletion-mode FET of the given polarity having a first source/drain element coupled to the supply of the substantially constant voltage, a gate electrode coupled to the output line, and a second source/drain element coupled to the feedback line.
Claim 18
Dependent Claim
31 words
A circuit as in claim 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, or 16 characterized in that each FET is an N-channel FET.
References Cited (Backward Citations)
US3806741A
Cited
US4229667A
Cited
US4388537A
Cited
US4336466A
Cited
US4344003A
Cited
US4322675A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-03-27 | 1987-09-26 | 1988-03-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-03-27 | 1991-09-26 | 1992-03-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-03-27 | 1995-09-26 | 1996-03-27 | $7700.00 | Window Closed / Lapsed |