US4229667A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Voltage boosting substrate bias generator
Assignee: Boeing North American Inc
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Filing: 1978-08-23
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Granted: 1980-10-21
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Expires: 1998-08-23
Abstract
Abstract An "on chip" substrate bias generator circuit to automatically compensate for threshold variations of devices that form a MOS circuit. The substrate bias generator includes a voltage doubler (or trippler) to develop a wide range of negative bias voltage to be fed back via the substrate to the MOS circuit to provide uniform bias control of the circuit devices.
Inventors
- 👤 Gary L. Heimbigner
- 👤 Robert K. Booher
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 09:36
CPC Classifications
G; G05; G05F; G05F3/00; G05F3/02; G05F3/08; G05F3/10; G05F3/16; G05F3/20; G05F3/205
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
230 words
A substrate bias generator circuit to develop a wide range of bias voltage to compensate for threshold variations in semiconductor devices that are formed on a substrate, said bias generator circuit comprising: transmission gate means, level detector means responsive to an input reference voltage signal, an output terminal of said level detector means connected to an input terminal of said transmission gate means; clock means for supplying a clock signal having first and second signal levels to another input terminal of said transmission gate means, signal level boosting means connected between an output terminal of said transmission gate means and the substrate, said signal level boosting means increasing the output signal level of said transmission gate means to be fed back to the semiconductor devices via the substrate; said signal level boosting means comprising first and second unidirectional current conducting means connected together in electrical series between a source of supply voltage and an electrical junction, inverter means, the output terminal of said transmission gate means connected to an input terminal of said inverter means, and first and second charge storage capacitance means, said first capacitance means connected between the output terminal of said transmission gate means and a point between the connection of said first and second unidirectional current conducting means, and said second capacitance means connected between an output terminal of said inverter means and said electrical junction.
Claim 2
Dependent Claim
230 words
A substrate bias generator circuit to develop a wide range of bias voltage to compensate for threshold variations in semiconductor devices that are formed on a substrate, said bias generator circuit comprising: transmission gate means, level detector means responsive to an input reference voltage signal, an output terminal of said level detector means connected to an input terminal of said transmission gate means; clock means for supplying a clock signal having first and second signal levels to another input terminal of said transmission gate means, signal level boosting means connected between an output terminal of said transmission gate means and the substrate, said signal level boosting means increasing the output signal level of said transmission gate means to be fed back to the semiconductor devices via the substrate; said signal level boosting means comprising first and second unidirectional current conducting means connected together in electrical series between a source of supply voltage and an electrical junction, inverter means, the output terminal of said transmission gate means connected to an input terminal of said inverter means, and first and second charge storage capacitance means, said first capacitance means connected between the output terminal of said transmission gate means and a point between the connection of said first and second unidirectional current conducting means, and said second capacitance means connected between an output terminal of said inverter means and said electrical junction.
Claim 3
Dependent Claim
31 words
The substrate bias generator circuit recited in claim 1, wherein said signal level boosting means further includes a third unidirectional current conducting means connected between said electrical junction and said substrate.
Claim 4
Dependent Claim
24 words
The substrate bias generator circuit recited in claim 2, wherein each of said first, second, and third unidirectional current conducting means is a diode.
Claim 5
Dependent Claim
39 words
The substrate bias generator circuit recited in claim 2, wherein each of said first, second, and third unidirectional current conducting means is a field effect transistor respectively having the control electrode and one conduction path electrode thereof connected together.
Claim 6
Dependent Claim
163 words
A voltage boosting substrate bias generator comprising: a substrate, transmission gate means to provide an output signal that is indicative of the bias voltage of said substrate, first and second unidirectional current conducting means connected together in electrical series between a source of supply voltage and an electrical junction, inverter means, the output terminal of said transmission gate means connected to an input terminal of said inverter means, first and second capacitance means, said first capacitance means connected between the output terminal of said transmission gate means and a point between the connection of said first and second unidirectional current conducting means, and said second capacitance means connected between an output terminal of said inverter means and said electrical junction, and third unidirectional current conducting means connected between said electrical junction and said substrate in order to supply said substrate with a bias voltage signal, the level of which signal is boosted relative to the output signal level of said transmission gate means.
Claim 7
Dependent Claim
163 words
A voltage boosting substrate bias generator comprising: a substrate, transmission gate means to provide an output signal that is indicative of the bias voltage of said substrate, first and second unidirectional current conducting means connected together in electrical series between a source of supply voltage and an electrical junction, inverter means, the output terminal of said transmission gate means connected to an input terminal of said inverter means, first and second capacitance means, said first capacitance means connected between the output terminal of said transmission gate means and a point between the connection of said first and second unidirectional current conducting means, and said second capacitance means connected between an output terminal of said inverter means and said electrical junction, and third unidirectional current conducting means connected between said electrical junction and said substrate in order to supply said substrate with a bias voltage signal, the level of which signal is boosted relative to the output signal level of said transmission gate means.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1983-10-21 | 1984-04-21 | 1984-10-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1987-10-21 | 1988-04-21 | 1988-10-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1991-10-21 | 1992-04-21 | 1992-10-21 | $7700.00 | Window Closed / Lapsed |