High frequency receive equalizer

Claim 2

A receive equalizer for restoring dispersed data pulses into a recoverable form, comprising: (a) an active filter having a single input for receiving the data pulses, a signal output and a control input; (b) a digital comparator, having a first input coupled to the signal output of the active filter and a second input coupled to a reference voltage, for comparing the signal output to the reference voltage, wherein the comparator provides a digital output indicating results of the comparison; and (c) feedback control means, having an input coupled to the digital output of the comparator and an output coupled to the control input of the active filter, for controlling capacitance values in the filter in response to the digital output of the comparator, wherein the feedback control means adjusts the filter gain and frequency selectivity in discrete steps until the signal output reaches a predetermined level.

Claim 3

The equalizer of claim 1, wherein the feedback control means comprises: (1) a random walk filter, having an input coupled to the output of the comparator and an output, for preventing dithering between steps when the equalizer has converged to a point where one step by the random walk filter would cause too little gain and a subsequent step would cause too much gain; (2) a sequencer, having an input coupled to a reference frequency clock and an output coupled to the output of the random walk filter, for sequencing the random walk filter; and (3) gain counter means, having an first input coupled to the output of the random walk filter, a second input coupled to the output of the sequencer for synchronization to a system clock, and an output coupled to the control input of the active filter, for switching capacitance within the active filter.

Claim 4

The equalizer of claim 2, wherein the feedback control means further comprising means for adjusting the gain and frequency selectivity of the active filter to approximate an inverse transfer function of a transmission line over which the received data pulses traverse.

Claim 5

The equalizer of claim 3, wherein the transmission line is a twisted pair cable.

Claim 6

The equalizer of claim 1, wherein the active filter comprises a plurality of individually adjustable discrete stages, wherein the stages are arranged in a monotonically increasing order.

Claim 7

The equalizer of claim 5, wherein the plurality of individually adjustable discrete transfer functions comprises: (i) a first stage having a differential input for coupling to the received data pulse and a differential output, the first stage providing a first transfer function having substantially flat frequency, adjustable coarse gain; (ii) a second stage having a differential input and a differential output, the second stage input being coupled to the first stage output and providing a second transfer function having high frequency, adjustable zeros; (iii) a third stage having a differential input and a differential output, the third stage input being coupled to the second stage output and providing a third transfer function having fixed high frequency attenuation; and (iv) a fourth stage having a differential input and a differential output, the fourth stage input being coupled to the third stage output, the fourth stage output being coupled to the comparator and providing an equalized data pulse, wherein the fourth stage provides a fourth transfer function having substantially flat frequency, adjustable fine gain.

Claim 8

The equalizer of claim 6, wherein the third stage comprises a plurality of transconductance cells and a plurality of capacitive elements arranged as a quasi-ladder structure.

Claim 9

The equalizer of claim 7, wherein each of the plurality of transconductance cells comprises: (a) a first MOS transistor having a first gate, a first drain and a first source; (b) a second MOS transistor having a second gate, a second drain and a second source, wherein the first and second gates are coupled as a differential input, and the first and second drains are coupled as a differential output; (c) a third MOS transistor having a third gate, a third drain coupled to the first source and a third source coupled to the second source, wherein the first and second MOS are coupled as a degenerated source-coupled pair, and the third gate is coupled as a control input for adjusting transconductance of the device; and (d) a plurality of MOS transistors for reducing output conductance, wherein the MOS transistors are coupled in a cascode fashion between the differential output and the first and second drains.

Claim 10

The equalizer of claim 8, wherein each of the plurality of transconductance cells further comprises calibration means, connected to the control input, for setting the transconductance of the device.

Claim 11

The equalizer of claim 6, wherein the second stage comprises at least one adjustable capacitive element, at least one fixed capacitive element, at least one transconductance cell and a high frequency operational amplifier, arranged as an active filter having at least one adjustable zero in combination with at least one fixed pole.

Claim 12

The equalizer of claim 10, wherein the adjustable capacitive element comprises a switchable array of capacitors having a logarithmically increasing capacitance ratio.

Claim 13

The equalizer of claim 6, wherein the first and fourth stages each comprise at least one adjustable capacitive element, at least one fixed capacitive element and a high frequency operational amplifier, arranged as a flat frequency, adjustable gain, active filter.