US4170758A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Process and device for the nonlinear equalization of digital signals
Assignee: Telecom Italia SpA
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Filing: 1977-06-23
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Granted: 1979-10-09
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Expires: 1997-06-23
Abstract
Abstract A receiver of digital signal pulses, operating with a sampling period T, comprises an equalizer which includes at least one feedback loop from the output of a decision unit for subtracting from an incoming signal pulse a value corresponding to the magnitude of a tail or postcursor of a preceding signal pulse. The signal pulse thus purged of postcursor interference is delayed by one or more sampling periods T for algebraic combination with one or more fed-forward compensating signals each representing the estimated value of an interfering precursor sample, these compensating signals being derived from the outputs of respective decision units with the aid of filters.
Inventors
- 👤 Giovanni Tamburelli
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 23:25
CPC Classifications
H; H04; H04L; H04L27/00; H04L27/01; H04L25/00; H04L25/02; H04L25/03; H04L25/03006; H04L25/03012; H04L25/03019; H04L25/03057
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
241 words
An equalizer for eliminating the effects of postcursor and precursor interference from a train of incoming digital signals, comprising: receiving means connected to a transmission path carrying said incoming signals; first threshold means connected to said receiving means for converting a given incoming signal into a first decided pulse having one of several predetermined signal levels; filter means connected to said first threshold means for deriving from said first decided pulse a feedback pulse adapted to correct postcursor interference and a feed-forward pulse adapted to compensate for precursor interference; first summing means inserted between said receiving means and said threshold means for algebraically combining said feedback pulse with a subsequent incoming signal; second summing means having an input connected to said filter means for receiving said feed-forward pulse therefrom; delay means connected to said receiving means for enbling an algebraic combination of said given signal with a concurrently arriving feed-forward pulse derived by said first threshold means and said filter means from said subsequent signal; second threshold means connected to said second summing means for converting an output pulse of the latter into a second decided pulse; and a circulator with an input connection to said filter means, an input/output connection to said delay means and an output connection to said second summing means for delivering said feedback pulse from said filter means to said first summing means and said given signal from said delay means to said second summing means.
Claim 2
Dependent Claim
241 words
An equalizer for eliminating the effects of postcursor and precursor interference from a train of incoming digital signals, comprising: receiving means connected to a transmission path carrying said incoming signals; first threshold means connected to said receiving means for converting a given incoming signal into a first decided pulse having one of several predetermined signal levels; filter means connected to said first threshold means for deriving from said first decided pulse a feedback pulse adapted to correct postcursor interference and a feed-forward pulse adapted to compensate for precursor interference; first summing means inserted between said receiving means and said threshold means for algebraically combining said feedback pulse with a subsequent incoming signal; second summing means having an input connected to said filter means for receiving said feed-forward pulse therefrom; delay means connected to said receiving means for enbling an algebraic combination of said given signal with a concurrently arriving feed-forward pulse derived by said first threshold means and said filter means from said subsequent signal; second threshold means connected to said second summing means for converting an output pulse of the latter into a second decided pulse; and a circulator with an input connection to said filter means, an input/output connection to said delay means and an output connection to said second summing means for delivering said feedback pulse from said filter means to said first summing means and said given signal from said delay means to said second summing means.
Claim 3
Dependent Claim
161 words
An equalizer as defined in claim 1 wherein said filter means, first threshold means, delay means, circulator and first summing means form part of a first cell; said second threshold means and second summing means being part of a second cell substantially identical with said first cell including other filter means connected to said second threshold means for deriving a second feed-forward pulse from said second decided pulse, a second circulator with an input connection to said other filter means, and other delay means forming part of a two-way connection between said second circulator one the one hand and the first-mentioned circulator and said second summing means on the other hand; further comprising third summing means having inputs connected to said other filter means and to said second circulator for algebraically combining said given signal with a concurrently arriving second feed-forward pulse derived by said first and second threshold means and by the first-mentioned filter means from a still-later incoming signal.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1982-10-08 | 1983-04-09 | 1983-10-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1986-10-08 | 1987-04-09 | 1987-10-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1990-10-08 | 1991-04-09 | 1991-10-09 | $7700.00 | Window Closed / Lapsed |