US4942370A
Expired / Lapsed
US
⏱️ 0.0 years remaining
PLL circuit with band width varying in accordance with the frequency of an input signal
Assignee: Ricoh Co Ltd
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Filing: 1989-04-04
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Granted: 1990-07-17
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Expires: 2009-04-04
Abstract
Abstract A PLL circuit comprises a phase comparator for inputting input and output clock signals and detecting a difference in phase between these both signals and outputting a signal based on the phase difference; a proportional circuit for converting the output signal based on the phase difference from the phase comparator to a first voltage approximately proportional to the phase difference; an integral circuit for converting the output signal based on the phase difference from one of the phase comparator and the proportional circuit to a second voltage approximately proportional to an integral value of the phase difference; and a voltage-controlled oscillator for inputting the first output voltage from the proportional circuit and the second output voltage from the integral circuit, and generating an output clock signal having a frequency controlled by the first and second output voltages. The proportional and integral circuits may be replaced in function by a signal processing circuit for performing predetermined data processing operations according to first and second operating states with respect to the data read operation, and an operational circuit having at least integral characteristics.
Inventors
- 👤 Toshihiro Shigemori
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 11:29
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/085; H03L7/093; H03L7/14; G; G11; G11B; G11B20/00; G11B20/10; G11B20/12; G11B20/1217; G11B20/1258; G11B20/14; G11B20/1403; H03L2207/00; H03L2207/04; H03L2207/06
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
148 words
A phase loop (PLL) circuit comprising: phase comparing means for receiving an input signal and an output clock signal, detecting a difference in phase between these two signals, and outputting a first signal according to said phase difference; proportional means for converting said first signal to a first voltage having an amplitude proportional to said phase difference; integral means for converting said first signal to a second voltage having an amplitude proportional to an integral value of said phase difference; and voltage-controlled oscillating meands for receiving said first and second voltages and generating said output clock signal having a frequency controlled by said first and second voltages, a frequency F 0 of said output clock signal being represented by the following formula, ##EQU8## where said first and second voltages are respectively designated by V 1 and V 2 , and the values, a, b, and c are constants.
Claim 2
Dependent Claim
148 words
A phase loop (PLL) circuit comprising: phase comparing means for receiving an input signal and an output clock signal, detecting a difference in phase between these two signals, and outputting a first signal according to said phase difference; proportional means for converting said first signal to a first voltage having an amplitude proportional to said phase difference; integral means for converting said first signal to a second voltage having an amplitude proportional to an integral value of said phase difference; and voltage-controlled oscillating meands for receiving said first and second voltages and generating said output clock signal having a frequency controlled by said first and second voltages, a frequency F 0 of said output clock signal being represented by the following formula, ##EQU8## where said first and second voltages are respectively designated by V 1 and V 2 , and the values, a, b, and c are constants.
Claim 3
Dependent Claim
216 words
A phase locked loop (PLL) circuit comprising: phase comparing means for receiving an input signal and an output clock signal, detecting a first difference in phase between these two signals, and outputting a first signal corresponding to said first phase difference; signal processing means for detecting a second difference in phase between said output clock signal and a reference clock signal having a predetermined frequency, outputting a second signal corresponding to said second phase difference while said PLL circuit is in a first state where no input signals are received by said phase comparing means, and outputting a third signal while said PLL circuit is in a second state where input signals are received by said phase comparing means, said third signal having a magnitude equal to an average value of the second signal outputted for a predetermined period just before said PLL circuit is changed to be in said second state from said first state; filter means for outputting a voltage signal corresponding to said second signal when said PLL circuit is in said first state, corresponding to a sum of said first signal and said third signal when said PLL circuit is in said second state; and voltage-controlled oscillating means for generating said output clock signal having a frequency corresponding to said voltage siganl.
Claim 4
Dependent Claim
216 words
A phase locked loop (PLL) circuit comprising: phase comparing means for receiving an input signal and an output clock signal, detecting a first difference in phase between these two signals, and outputting a first signal corresponding to said first phase difference; signal processing means for detecting a second difference in phase between said output clock signal and a reference clock signal having a predetermined frequency, outputting a second signal corresponding to said second phase difference while said PLL circuit is in a first state where no input signals are received by said phase comparing means, and outputting a third signal while said PLL circuit is in a second state where input signals are received by said phase comparing means, said third signal having a magnitude equal to an average value of the second signal outputted for a predetermined period just before said PLL circuit is changed to be in said second state from said first state; filter means for outputting a voltage signal corresponding to said second signal when said PLL circuit is in said first state, corresponding to a sum of said first signal and said third signal when said PLL circuit is in said second state; and voltage-controlled oscillating means for generating said output clock signal having a frequency corresponding to said voltage siganl.
Claim 5
Dependent Claim
24 words
A PLL circuit according to claim 2, in which said filter means has a characteristic of integrating an input signal in a low-frequency range.
Claim 6
Dependent Claim
23 words
A PLL circuit according to claim 2, in which said signal processing means is provided with a digital-to-analog converter at an output thereof.
Claim 7
Dependent Claim
38 words
A PLL circuit according to claim 2, in which said phase comparing means is provided with gate means which allows the first signal to pass to said filter means when said PLL circuit is in said second state.
Claim 8
Dependent Claim
253 words
A phase locked loop (PLL) circuit comprising: phase comparing means for receiving an input signal and an output clock signal, detecting a first difference in phase between these two signals, and outputting a first signal corresponding to said first phase difference; proportional means for converting the first signal to a first voltage signal having an amplitude proportional to said phase difference; signal processing means for detecting a second difference in phase between said output clock signal and a reference clock signal having a predetermined frequency, outputting a second signal corresponding to said second phase difference while said PLL circuit is in a first state where on input signals are received by said phase comparing means, and outputting a third signal while said PLL circuit is in a second state where input signals are received by said phase comparing means, said third signal having a magnitude equal to an average value of the second signal outputted for a predetermined period just before said PLL circuit is changed to be in said second state from said first state; integral means for integrating said second signal thereby producing a second voltage when said PLL circuit is in said first state and integrating a sum of said first signal and said third signal thereby producing a third voltage signal; and voltage-controlled oscillating means for receiving said first, second and third voltage signals and for generating said output clock signal having a frequency corresponding to said first and second voltage signals or said first and third voltage signals.
Claim 9
Dependent Claim
253 words
A phase locked loop (PLL) circuit comprising: phase comparing means for receiving an input signal and an output clock signal, detecting a first difference in phase between these two signals, and outputting a first signal corresponding to said first phase difference; proportional means for converting the first signal to a first voltage signal having an amplitude proportional to said phase difference; signal processing means for detecting a second difference in phase between said output clock signal and a reference clock signal having a predetermined frequency, outputting a second signal corresponding to said second phase difference while said PLL circuit is in a first state where on input signals are received by said phase comparing means, and outputting a third signal while said PLL circuit is in a second state where input signals are received by said phase comparing means, said third signal having a magnitude equal to an average value of the second signal outputted for a predetermined period just before said PLL circuit is changed to be in said second state from said first state; integral means for integrating said second signal thereby producing a second voltage when said PLL circuit is in said first state and integrating a sum of said first signal and said third signal thereby producing a third voltage signal; and voltage-controlled oscillating means for receiving said first, second and third voltage signals and for generating said output clock signal having a frequency corresponding to said first and second voltage signals or said first and third voltage signals.
Claim 10
Dependent Claim
23 words
A PLL circuit according to claim 6, in which said signal processing means is provided with a digital-to-analog converter at an output thereof.
Claim 11
Dependent Claim
38 words
A PLL circuit according to claim 6, in which said phase comparing means is provided with gate means which allows the first signal to pass to said proportional means when said PLL circuit is in said second state.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-07-16 | 1994-01-15 | 1994-07-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-07-16 | 1998-01-15 | 1998-07-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-07-16 | 2002-01-15 | 2002-07-17 | $7700.00 | Window Closed / Lapsed |