US5480841A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Process of multilayer conductor chip packaging
Assignee: GlobalFoundries Inc
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Filing: 1994-09-07
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Granted: 1996-01-02
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Expires: 2014-09-07
Abstract
Abstract A process of providing an external wiring and connecting package for a semiconductor chip wherein the chip is a major contributor to the strength of the package. External contacts and wiring are provided by a multilayer wiring member that may include a mesh ground plane with embedded power bus layer over a conductor layer for expansion mismatch control and impedance control, a protective encapsulation covers the bonds from the wiring conductors to the chip, and external contact connections employ fused metal through the contact members.
Inventors
- 👤 Harry R. Bickford
- 👤 Paul W. Coteus
- 👤 Linda C. Matthew
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 17:02
CPC Classifications
H; H05; H05K; H05K3/00; H05K3/30; H05K3/32; H05K3/34; H05K3/341; H05K3/3421; H05K3/3426; H10; H10W; H10W70/00; H10W70/40; H10W70/411; H10W70/415; H10W70/451; H10W70/453; H10W70/60; H10W70/67; H10W70/68; H10W70/685; H10W72/00; H05K2201/00; H05K2201/10; H05K2201/10431; H05K2201/10568; H05K2201/10613; H05K2201/10621; H05K2201/10681; H05K2201/10689; H10W72/50; H10W72/531; H10W72/536; H10W72/5366; H10W72/851; H10W72/853; H10W72/865; H10W72/90; H10W72/931; H10W72/932; H10W72/951; H10W74/00; H10W90/00; H10W90/701; H10W90/751; H10W90/754; H10W90/756; Y; Y02; Y02P; Y02P70/00; Y02P70/50; Y10; Y10T; Y10T29/00; Y10T29/49; Y10T29/49002; Y10T29/49117; Y10T29/49121
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
117 words
The process of manufacturing a semiconductor chip package comprising in combination the steps of: providing a multi layer wiring member having at least one combination of a wiring layer and a broad metal layer separated by a layer of dielectric, isolating at least one portion of said broad metal layer from the remaining portions of said broad metal layer, positioning a portion of said wiring layer of said multi layer wiring member adjacent the chip connection pads on a surface of said chip, joining with a conductive bond member at least one conductor of said wiring layer to at least one chip connection pad, and, encapsulating said bonds, said chip surface and said multi layer wiring member.
Claim 2
Dependent Claim
117 words
The process of manufacturing a semiconductor chip package comprising in combination the steps of: providing a multi layer wiring member having at least one combination of a wiring layer and a broad metal layer separated by a layer of dielectric, isolating at least one portion of said broad metal layer from the remaining portions of said broad metal layer, positioning a portion of said wiring layer of said multi layer wiring member adjacent the chip connection pads on a surface of said chip, joining with a conductive bond member at least one conductor of said wiring layer to at least one chip connection pad, and, encapsulating said bonds, said chip surface and said multi layer wiring member.
Claim 3
Dependent Claim
36 words
The process of claim 1 including the step of: providing a connection through said dielectric layer connecting at least one selected isolated portion of said broad metal layer with at least one conductor in wiring layer.
Claim 4
Dependent Claim
40 words
The process of claim 1 wherein, in said joining step, each said conductive bond from a chip connection pad to a conductor in said wiring layer, is shaped to be closer to said chip surface than said broad metal layer.
Claim 5
Dependent Claim
52 words
The process of claim 3 wherein said encapsulating step includes the steps of: surrounding said bonds with a bond encapsulant extending from the surface of said chip to level with the top of said broad metal layer, and covering said multilayer wiring member and said bond encapsulant with a covering plastic material.
Claim 6
Dependent Claim
21 words
The process of claim 4 including the step of punching out external contact members from portions of said multilayer wiring member.
Claim 7
Dependent Claim
177 words
The process of manufacturing a semiconductor chip package comprising in combination the steps of: positioning a semiconductor chip in a surface area of a supporting base with the connector pad surface of said chip flush with the surface of said base, positioning a multi layer wiring member having superimposed layers of wiring conductors and of broad metal separated by a layer of dielectric, with said wiring conductor layer on said base and proximate the connector pads on said chip, isolating at least one portion of said broad metal layer from the remaining portions of said broad metal layer, connecting at least one selected isolated portion of said broad metal layer to at least one conductor in said wiring layer with a via through said dielectric layer, providing bond members joining conductors on said wiring layer to adjacent pads on said chip, surrounding said bonds with a bond encapsulant extending from the surface of said chip to the top of said broad metal layer, and, covering said multilayer wiring member and said bond encapsulant with a covering material.
Claim 8
Dependent Claim
177 words
The process of manufacturing a semiconductor chip package comprising in combination the steps of: positioning a semiconductor chip in a surface area of a supporting base with the connector pad surface of said chip flush with the surface of said base, positioning a multi layer wiring member having superimposed layers of wiring conductors and of broad metal separated by a layer of dielectric, with said wiring conductor layer on said base and proximate the connector pads on said chip, isolating at least one portion of said broad metal layer from the remaining portions of said broad metal layer, connecting at least one selected isolated portion of said broad metal layer to at least one conductor in said wiring layer with a via through said dielectric layer, providing bond members joining conductors on said wiring layer to adjacent pads on said chip, surrounding said bonds with a bond encapsulant extending from the surface of said chip to the top of said broad metal layer, and, covering said multilayer wiring member and said bond encapsulant with a covering material.
Claim 9
Dependent Claim
43 words
The process of claim 6 wherein, in said providing bond members step, each said bond from a chip pad to a conductor in said wiring layer, is shaped to be closer to said chip surface than the top of said broad metal layer.
Claim 10
Dependent Claim
27 words
The process of claim 6 including the step of punching out external contact members from portions of said multilayer wiring member extending beyond said base surface area.
Claim 11
Dependent Claim
194 words
The processor manufacturing an external wiring connecting and supporting package for a semiconductor chip, comprising the steps of: providing a multilayer wiring member having superimposed layers of wiring conductor metal and broad metal separated by a layer of dielectric, and having an area opening corresponding to an area of pads in the surface of said chip, isolating at least one portion of said broad metal layer from the remaining portions of said broad metal layer, connecting at least one selected isolated portion of said broad metal layer to at least one conductor in said wiring layer with a via through said dielectric layer, positioning said multilayer wiring member with said wiring conductor metal layer next to said semiconductor chip and with said pad area of said chip surrounded by said opening, connecting at least one bond member from at least one pad area in the surface of said chip to at least one wiring conductor in said wiring conductor metal layer, forming portions of said multilayer wiring member in locations separated from said opening into external conductor portions, and, connecting at least one said external conductor portion to at least one external wiring connection.
Claim 12
Dependent Claim
194 words
The processor manufacturing an external wiring connecting and supporting package for a semiconductor chip, comprising the steps of: providing a multilayer wiring member having superimposed layers of wiring conductor metal and broad metal separated by a layer of dielectric, and having an area opening corresponding to an area of pads in the surface of said chip, isolating at least one portion of said broad metal layer from the remaining portions of said broad metal layer, connecting at least one selected isolated portion of said broad metal layer to at least one conductor in said wiring layer with a via through said dielectric layer, positioning said multilayer wiring member with said wiring conductor metal layer next to said semiconductor chip and with said pad area of said chip surrounded by said opening, connecting at least one bond member from at least one pad area in the surface of said chip to at least one wiring conductor in said wiring conductor metal layer, forming portions of said multilayer wiring member in locations separated from said opening into external conductor portions, and, connecting at least one said external conductor portion to at least one external wiring connection.
Claim 13
Dependent Claim
17 words
The process of claim 9 including the step of filling said opening with a bond protecting encapsulant.
Claim 14
Dependent Claim
27 words
The process or claim 9 including the step of providing in said broad metal layer a surrounded area of metal electrically separated from said broad metal layer.
Claim 15
Dependent Claim
46 words
The process of claim 9 including the step of providing a separation region in said broad metal area metal layer that electrically separates at least one selected said external conductor portion of said broad area metal layer from the remainder of said broad area metal layer.
Claim 16
Dependent Claim
40 words
The process of claim 11 including the step of providing at least one via connection through said dielectric interconnecting at least one of a conductor in said wiring conductor layer, said surrounded area of metal and said broad metal layer.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-01-01 | 1999-07-03 | 2000-01-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-01-01 | 2003-07-03 | 2004-01-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-01-01 | 2007-07-03 | 2008-01-02 | $7700.00 | Window Closed / Lapsed |