US5369059A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method for constructing a reduced capacitance chip carrier
Assignee: Cray Inc
•
Filing: 1992-04-08
•
Granted: 1994-11-29
•
Expires: 2012-04-08
Abstract
Abstract A method for making an integrated circuit chip carrier having reduced and regulable interlead capacitance and reduced glass chip formation. The chip carrier includes a substrate having a central cavity for locating an integrated circuit die, an inner channel and an outer channel, adhesive glass located in the channels and overflowing above the substrate surface, a leadframe mounted on the substrate having a plurality of leads embedded in the adhesive glass overflow and coplanarly resting on the substrate, the leads extending from beyond the substrate periphery inward to near the cavity rim, and a thin layer of sealing glass extending from the periphery of the substrate over the outer channel for hermetically sealing the chip carrier.
Inventors
- 👤 Delvin D. Eberlein
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 23:17
CPC Classifications
H; H10; H10W; H10W70/00; H10W70/40; H10W70/479; H10W70/60; H10W70/67; H10W70/68; H10W70/69; H10W70/698; Y; Y10; Y10T; Y10T156/00; Y10T156/10; Y10T156/1002; Y10T29/00; Y10T29/49; Y10T29/49002; Y10T29/49117; Y10T29/49121; Y10T29/49124; Y10T29/49147
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
190 words
A method of constructing a chip carrier, comprising the steps of: (a) providing a substrate having a substantially planar surface, said substrate forming a part of said chip carrier; (b) creating on said planar surface at a centrally located position a cavity for subsequently locating an integrated circuit die; (c) creating a first channel in said surface concentric to said cavity; (d) creating a second channel in said surface concentric to said first channel; (e) creating a third channel in said surface concentric to said second channel; (f) depositing and substantially confining adhesive glass in said first channel and said second channel by placing a layer of adhesive glass on said first channel and said second channel; (g) attaching a plurality of leads to said planar surface by placing said plurality of leads on said planar surface so that said adhesive glass secures said leads to said substrate, and further so that said leads contact said planar surface on each side of each of said first, second and third channels; and (h) providing said third channel with an air space beneath a portion of said leads in said chip carrier.
Claim 2
Independent Claim
190 words
A method of constructing a chip carrier, comprising the steps of: (a) providing a substrate having a substantially planar surface, said substrate forming a part of said chip carrier; (b) creating on said planar surface at a centrally located position a cavity for subsequently locating an integrated circuit die; (c) creating a first channel in said surface concentric to said cavity; (d) creating a second channel in said surface concentric to said first channel; (e) creating a third channel in said surface concentric to said second channel; (f) depositing and substantially confining adhesive glass in said first channel and said second channel by placing a layer of adhesive glass on said first channel and said second channel; (g) attaching a plurality of leads to said planar surface by placing said plurality of leads on said planar surface so that said adhesive glass secures said leads to said substrate, and further so that said leads contact said planar surface on each side of each of said first, second and third channels; and (h) providing said third channel with an air space beneath a portion of said leads in said chip carrier.
Claim 3
Dependent Claim
28 words
The method according to claim 1 further including the step of applying a sealing compound on top of said plurality of leads at the periphery of said substrate.
Claim 4
Independent Claim
193 words
A method of forming a reduced-capacitance chip carrier, comprising the steps of: (a) providing a substrate having a substantially planar surface and a defined periphery, said substrate forming a part of said chip carrier; (b) depressing a cavity in said surface for locating an integrated circuit die; (c) depressing a first channel in said surface between said periphery and said cavity; (d) depressing a second channel in said surface between said periphery and said cavity and adjacent to said first channel; (e) depositing and substantially confining an adhesive glass in said first channel by placing a layer of said adhesive glass on said first channel; (f) placing a leadframe comprising a plurality of leads on said surface so that at least a portion said leads bridge each of said first and second channels and so that the portion of said leads bridging said first channel is in contact with said adhesive glass, and further so that said leads contact said planar surface on each side of each of said first and second channels; and (g) providing said second channel with an air space beneath a portion of said leads in said chip carrier.
Claim 5
Independent Claim
193 words
A method of forming a reduced-capacitance chip carrier, comprising the steps of: (a) providing a substrate having a substantially planar surface and a defined periphery, said substrate forming a part of said chip carrier; (b) depressing a cavity in said surface for locating an integrated circuit die; (c) depressing a first channel in said surface between said periphery and said cavity; (d) depressing a second channel in said surface between said periphery and said cavity and adjacent to said first channel; (e) depositing and substantially confining an adhesive glass in said first channel by placing a layer of said adhesive glass on said first channel; (f) placing a leadframe comprising a plurality of leads on said surface so that at least a portion said leads bridge each of said first and second channels and so that the portion of said leads bridging said first channel is in contact with said adhesive glass, and further so that said leads contact said planar surface on each side of each of said first and second channels; and (g) providing said second channel with an air space beneath a portion of said leads in said chip carrier.
References Cited (Backward Citations)
DE214494C
Cited
US3103061A
Cited
US4043027A
Cited
US3484534A
Cited
JPS56103435A
Cited
US4355463A
Cited
FR2514123A1
Cited
US4556896A
Cited
JPS60103647A
Cited
US4611398A
Cited
JPS61196585A
Cited
US4729010A
Cited
US4792773A
Cited
US4701999A
Cited
US4722137A
Cited
US4783358A
Cited
US4820658A
Cited
JPS63249394A
Cited
JPS63288029A
Cited
JPS63306646A
Cited
JPH01125853A
Cited
US4931854A
Cited
US5134247A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-11-28 | 1998-05-30 | 1998-11-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-11-28 | 2002-05-30 | 2002-11-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-11-28 | 2006-05-30 | 2006-11-29 | $7700.00 | Window Closed / Lapsed |