US5468664A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of making semiconductor device with alignment marks
Assignee: Fujitsu Ltd
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Filing: 1994-11-16
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Granted: 1995-11-21
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Expires: 2014-11-16
Abstract
Abstract A semiconductor device includes a base layer, a chip region formed on the base layer, a peripheral region which surrounds the chip region on the base layer, and a patterned stacked structure formed on the base layer in both the chip region and the peripheral region. The patterned stacked structure includes a lower layer which is formed on the base layer, an intermediate layer which is formed on the lower layer and an upper layer formed on the intermediate layer. The upper layer and the intermediate layer are aligned to one side surface of the lower layer in at least a part of the chip region. The intermediate layer and the upper layer cover one side surface of the lower layer in at least a part of the peripheral region.
Inventors
- 👤 Tatsuya Kajita
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 18:30
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/68; H10D30/681; H10D64/00; H10D64/01; H10D64/031; H10D64/035; H10D64/60; H10D64/66; H10D64/68; H10D64/689; H10P; H10P14/00; H10P14/40; H10P14/416; H10P76/00; H10P76/20; H10P76/204; Y; Y10; Y10S; Y10S148/00; Y10S148/102; Y10S438/00; Y10S438/975
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
187 words
A method of producing a semiconductor device comprising the steps of: preparing a stacked structure including a base layer, a patterned lower layer formed on a surface of said base layer, an intermediate layer which covers the surface of said base layer in its entirety including said lower layer, and an upper layer which covers a surface of said intermediate layer in its entirety, said lower layer having an etching rate greater than an etching rate of said intermediate layer; patterning said upper and lower layers in a chip region containing electrically coupled elements that form part of an electric circuit on said base layer so that said upper layer and said intermediate layer are aligned to one side surface of said lower layer in at least a part of said chip region; and patterning said upper layer in a peripheral region including no elements which form said electric circuit so that said intermediate layer and said upper layer cover one side surface of said lower layer in at least a part of said peripheral region, said peripheral region surrounding said chip region on said base layer.
Claim 2
Independent Claim
187 words
A method of producing a semiconductor device comprising the steps of: preparing a stacked structure including a base layer, a patterned lower layer formed on a surface of said base layer, an intermediate layer which covers the surface of said base layer in its entirety including said lower layer, and an upper layer which covers a surface of said intermediate layer in its entirety, said lower layer having an etching rate greater than an etching rate of said intermediate layer; patterning said upper and lower layers in a chip region containing electrically coupled elements that form part of an electric circuit on said base layer so that said upper layer and said intermediate layer are aligned to one side surface of said lower layer in at least a part of said chip region; and patterning said upper layer in a peripheral region including no elements which form said electric circuit so that said intermediate layer and said upper layer cover one side surface of said lower layer in at least a part of said peripheral region, said peripheral region surrounding said chip region on said base layer.
Claim 3
Dependent Claim
32 words
The method as claimed in claim 1 wherein said base layer is formed on a substrate, said base layer having an etching rate greater than the etching rate of said intermediate layer.
Claim 4
Dependent Claim
24 words
The method as claimed in claim 1 wherein said upper layer has an etching rate greater than an etching rate of said lower layer.
Claim 5
Dependent Claim
27 words
The method as claimed in claim 1 wherein said upper and lower layers are made of a material selected from a group consisting of polysilicon and polycide.
Claim 6
Dependent Claim
15 words
The method as claimed in claim 1 wherein said base layer is SiO 2 .
Claim 7
Dependent Claim
29 words
The method as claimed in claim 1 wherein said intermediate layer is made of a material selected from a group consisting of SiN and Ta 2 O 3 .
Claim 8
Dependent Claim
24 words
The method as claimed in claim 1 wherein said two patterning steps use an anisotropic dry etching for etching at least said intermediate layer,
Claim 9
Independent Claim
183 words
A method of producing a semiconductor device comprising the steps of: forming a lower layer on a surface of a base layer; patterning said lower layer to expose side surfaces of said lower layer and parts of the surface of said base layer; forming an intermediate layer which covers the surface of said base layer in its entirety including said lower layer, said intermediate layer having an etching rate smaller than an etching rate of said lower layer; forming an upper layer which covers a surface of said intermediate layer in its entirety; and patterning said upper layer so that said upper layer and said intermediate layer are aligned to one side surface of said lower layer in at least a part of a chip region containing electrically coupled elements that form part of an electric circuit on said base layer and said intermediate layer and said upper layer cover one side surface of said lower layer in at least a part of a peripheral region which surrounds said chip region including no elements which form said electric circuit on said base layer.
Claim 10
Independent Claim
183 words
A method of producing a semiconductor device comprising the steps of: forming a lower layer on a surface of a base layer; patterning said lower layer to expose side surfaces of said lower layer and parts of the surface of said base layer; forming an intermediate layer which covers the surface of said base layer in its entirety including said lower layer, said intermediate layer having an etching rate smaller than an etching rate of said lower layer; forming an upper layer which covers a surface of said intermediate layer in its entirety; and patterning said upper layer so that said upper layer and said intermediate layer are aligned to one side surface of said lower layer in at least a part of a chip region containing electrically coupled elements that form part of an electric circuit on said base layer and said intermediate layer and said upper layer cover one side surface of said lower layer in at least a part of a peripheral region which surrounds said chip region including no elements which form said electric circuit on said base layer.
Claim 11
Dependent Claim
32 words
The method as claimed in claim 8 wherein said base layer is formed on a substrate, said base layer having an etching rate greater than the etching rate of said intermediate layer.
Claim 12
Dependent Claim
24 words
The method as claimed in claim 8 wherein said upper layer has an etching rate greater than an etching rate of said lower layer.
Claim 13
Dependent Claim
27 words
The method as claimed in claim 8 wherein said upper and lower layers are made of a material selected from a group consisting of polysilicon and polycide.
Claim 14
Dependent Claim
15 words
The method as claimed in claim 8 wherein said base layer is SiO 2 .
Claim 15
Dependent Claim
29 words
The method as claimed in claim 8 wherein said intermediate layer is made of a material selected from a group consisting of SiN and Ta 2 O 3 .
Claim 16
Dependent Claim
24 words
The method as claimed in claim 8 wherein said two patterning steps use an anisotropic dry etching for etching at least said intermediate layer.
Claim 17
Dependent Claim
51 words
The method as claimed in claim 8 wherein said step of patterning said upper layer intensionally leaves a patterned stacked structure on said base layer in said peripheral region, said intermediate layer and said upper layer of said patterned stacked structure covering at least one side surface of said lower layer.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-11-20 | 1999-05-22 | 1999-11-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-11-20 | 2003-05-22 | 2003-11-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-11-20 | 2007-05-22 | 2007-11-21 | $7700.00 | Window Closed / Lapsed |