Thin film transistor array

Claim 2

A thin film transistor array comprising: a substrate; a plurality of thin film transistors arranged in a shape of an array on said substrate, said thin film transistors each including, a gate electrode formed on said substrate, a first insulating layer formed over said gate electrode and said substrate, a semiconducting layer formed on a first portion of said first insulating layer, a second insulating layer formed on a second portion of said semiconducting layer wherein the area of said second portion is smaller than the area of said first portion, and a source/drain layer formed over each of the previously formed said layers and forming a source electrode and a drain electrode for each transistor; a gate bus bar for commonly connecting at least some of said gate electrodes; and a source bus bar for commonly connecting at least some of said source electrodes; said source bus bar and said gate bus bar intersecting at an intersectional overlay area of said array associated with a said thin film transistor; said first insulating layer, said semiconducting layer and said second insulating layer of each said transistor extending across said substrate and into said intersectional overlay area so as to prevent leakage between said gate bus bar and said source bus bar at said intersectional overlay area; said first and second portions being formed to smooth the transition between the surface of said substrate and the surface of said first insulating layer to reduce the gradient over which said source/drain layer must be applied to reduce possible breakage of said source/drain layer. PG,20

Claim 3

A thin film transistor array as claimed in claim 1, wherein said semiconducting layer is made of amorphous silicon.

Claim 4

A thin film transistor array as claimed in claim 1, wherein said first insulating layer and said second insulating layer are made of silicon nitride.

Claim 5

A thin film transistor array as claimed in claim 1, wherein said first insulating layer and said second insulating layer are made of silicon oxide.

Claim 6

a thin film transistor array comprising: a substrate; a gate electrode bus formed on said substrate for connecting a predetermined number of a plurality of gate electrodes in the thin film transistor array; a gate insulating film formed over said gate electrode bus; a semiconducting film formed on a portion of said gate insulating film; a protective insulating film formed on said semiconducting film; and a source electrode bus for connecting a predetermined number of a plurality of source electrodes in the thin film array that is formed on said gate insulating film, said semiconducting film and said protective insulating film, said source electrode bus and said gate electrode bus intersecting at an intersectional overlay area of the array; said gate insulating film, said semiconducting film and said protective insulating film being interposed between said gate electrode bus and said source electrode bus at said intersectional; said gate insulating film having a peripheral edge around at least a substantial portion of said intersectional overlay area; said semiconductor film having a peripheral edge around said substantial portion of said intersectional overlay area, said peripheral edge of said semiconducting film being inside of said peripheral edge of said gate insulating film to form a first step; said protective insulating film having a peripheral edge around said substantial portion of said intersectional overlay area, said peripheral edge of said protective insulating film being inside of said peripheral edge of said semiconducting film to form a second step; said first and second steps smoothing the transition between the surface of said substrate and the surface of said gate insulating film to reduce the gradient over which said source electrode bus must be applied to reduce possible breakage of said source electrode bus.

Claim 7

a thin film transistor array comprising: a substrate; a gate electrode bus formed on said substrate for connecting a predetermined number of a plurality of gate electrodes in the thin film transistor array; a gate insulating film formed over said gate electrode bus; a semiconducting film formed on a portion of said gate insulating film; a protective insulating film formed on said semiconducting film; and a source electrode bus for connecting a predetermined number of a plurality of source electrodes in the thin film array that is formed on said gate insulating film, said semiconducting film and said protective insulating film, said source electrode bus and said gate electrode bus intersecting at an intersectional overlay area of the array; said gate insulating film, said semiconducting film and said protective insulating film being interposed between said gate electrode bus and said source electrode bus at said intersectional; said gate insulating film having a peripheral edge around at least a substantial portion of said intersectional overlay area; said semiconductor film having a peripheral edge around said substantial portion of said intersectional overlay area, said peripheral edge of said semiconducting film being inside of said peripheral edge of said gate insulating film to form a first step; said protective insulating film having a peripheral edge around said substantial portion of said intersectional overlay area, said peripheral edge of said protective insulating film being inside of said peripheral edge of said semiconducting film to form a second step; said first and second steps smoothing the transition between the surface of said substrate and the surface of said gate insulating film to reduce the gradient over which said source electrode bus must be applied to reduce possible breakage of said source electrode bus.

Claim 8

A thin film transistor array as claimed in claim 5, wherein said semiconducting film is made of amorphous silicon.