Method of manufacturing logic semiconductor device having non-volatile memory

Claim 1

A method of manufacturing a semiconductor device in which a non-volatile memory and a logic circuit portion are formed on a single semiconductor substrate, comprising the steps of: forming a first insulating film which is to serve as an element isolating region on a surface of a semiconductor substrate; partially removing said first insulating film to form a forming region for a memory cell portion and a forming region for a logic circuit portion on said substrate; forming a second insulating film which is to serve as a first gate insulating film of a cell transistor of said memory cell portion on an entire surface of a resultant structure; doping an impurity for controlling a threshold value of said cell transistor in a channel region of said cell transistor of said memory cell portion; forming a first conductive layer on an entire surface; patterning said first conductive layer to form a floating gate of said memory cell portion and to expose said logic circuit portion forming region; forming a laminated insulating layer consisting of a plurality of insulating films on an entire surface of a resultant structure by sequentially forming a first oxide film and a first nitride film, oxidizing a surface of said nitride film to form a second oxide film, and forming a second nitride film; patterning said laminated insulating layer to expose said logic circuit portion forming region on the substrate; forming a second insulating film which is to serve as a sacrificial oxide film of said logic circuit portion on an entire surface of a resultant structure; doping an impurity for controlling a threshold value of a transistor of said logic circuit portion in said logic circuit portion through said second insulating film; removing said second insulating film; forming a third insulating film on an entire surface of a resultant structure; forming a second conductive layer on an entire surface of a resultant structure; and sequentially patterning said second conductive layer and said third insulating film to form a control gate of said memory cell portion and to form a gate of said transistor of said logic circuit portion.

Claim 2

A method of manufacturing a semiconductor device in which a non-volatile memory and a logic circuit portion are formed on a single semiconductor substrate, comprising the steps of: forming a first insulating film which is to serve as an element isolating region on a surface of a semiconductor substrate; partially removing said first insulating film to form a forming region for a memory cell portion and a forming region for a logic circuit portion on said substrate; forming a second insulating film which is to serve as a first gate insulating film of a cell transistor of said memory cell portion on an entire surface of a resultant structure; doping an impurity for controlling a threshold value of said cell transistor in a channel region of said cell transistor of said memory cell portion; forming a first conductive layer on an entire surface; patterning said first conductive layer to form a floating gate of said memory cell portion and to expose said logic circuit portion forming region; forming a laminated insulating layer consisting of a plurality of insulating films on an entire surface of a resultant structure by sequentially forming a first oxide film and a first nitride film, oxidizing a surface of said nitride film to form a second oxide film, and forming a second nitride film; patterning said laminated insulating layer to expose said logic circuit portion forming region on the substrate; forming a second insulating film which is to serve as a sacrificial oxide film of said logic circuit portion on an entire surface of a resultant structure; doping an impurity for controlling a threshold value of a transistor of said logic circuit portion in said logic circuit portion through said second insulating film; removing said second insulating film; forming a third insulating film on an entire surface of a resultant structure; forming a second conductive layer on an entire surface of a resultant structure; and sequentially patterning said second conductive layer and said third insulating film to form a control gate of said memory cell portion and to form a gate of said transistor of said logic circuit portion.

Claim 3

A method of manufacturing a semiconductor device in which a non-volatile memory and a logic circuit portion are formed on a single semiconductor substrate, comprising the steps of: forming a first insulating film which is to serve as an element isolating region on a surface of a semiconductor substrate; partially removing said first insulating film to form a forming region of a memory cell portion and a forming region of a logic circuit portion of said substrate; forming a second insulating film which is to serve as a first gate insulating film of a cell transistor of said memory cell portion on an entire surface of a resultant structure; doping an impurity for controlling a threshold value of said cell transistor in a channel region of said cell transistor of said memory cell portion; forming a first conductive layer on an entire surface; patterning said first conductive layer to form a floating gate of said memory cell portion and to expose said logic circuit portion forming region; sequentially forming a first oxide film, a first nitride film, a second oxide film and a second nitride film; sequentially patterning said second nitride film, said second oxide film, said first nitride film and said first oxide film to expose said logic circuit portion forming region on the substrate; forming a second insulating film which is to serve as a sacrificial oxide film of said logic circuit portion on an entire surface of a resultant structure; doping an impurity for controlling a threshold value of a transistor of said logic circuit portion in said logic circuit portion through said second insulating film; removing said second insulating film; forming a third insulating film on an entire surface of a resultant structure; forming a second conductive layer on an entire surface of a resultant structure; and sequentially patterning said conductive layer and said third insulating film to form a control gate of said memory cell portion and to form a gate of said transistor of said logic circuit portion.

Claim 4

A method of manufacturing a semiconductor device in which a non-volatile memory and a logic circuit portion are formed on a single semiconductor substrate, comprising the steps of: forming a first insulating film which is to serve as an element isolating region on a surface of a semiconductor substrate; partially removing said first insulating film to form a forming region of a memory cell portion and a forming region of a logic circuit portion of said substrate; forming a second insulating film which is to serve as a first gate insulating film of a cell transistor of said memory cell portion on an entire surface of a resultant structure; doping an impurity for controlling a threshold value of said cell transistor in a channel region of said cell transistor of said memory cell portion; forming a first conductive layer on an entire surface; patterning said first conductive layer to form a floating gate of said memory cell portion and to expose said logic circuit portion forming region; sequentially forming a first oxide film, a first nitride film, a second oxide film and a second nitride film; sequentially patterning said second nitride film, said second oxide film, said first nitride film and said first oxide film to expose said logic circuit portion forming region on the substrate; forming a second insulating film which is to serve as a sacrificial oxide film of said logic circuit portion on an entire surface of a resultant structure; doping an impurity for controlling a threshold value of a transistor of said logic circuit portion in said logic circuit portion through said second insulating film; removing said second insulating film; forming a third insulating film on an entire surface of a resultant structure; forming a second conductive layer on an entire surface of a resultant structure; and sequentially patterning said conductive layer and said third insulating film to form a control gate of said memory cell portion and to form a gate of said transistor of said logic circuit portion.