Nonvolatile semiconductor memory and manufacture therefor

Abstract

Abstract PURPOSE: To prevent the extension of writing time and incorrect writing by a method wherein the overlapping portion of the floating gate and the drain of an IG-FET forming a memory cell is made shorter than an IG-FET on the same substrate. CONSTITUTION: An N + type source S and a drain D are made with a control gate CG as a mask, and N + layers 12, 13 of an IG-FET 11 of the peripheral circuit of a cell array are formed with a gate 14 as a mask. With this construction, the N + layers S, D right under a floating gate FG are made shorter than the case of employing the FG as a mask, while the diffusing distance in the transverse direction from the FG standpoint is smaller than x j of the FET11, thus reducing capacitance. For this reason, the floating gate potential of the nonselective memory cell becomes smaller, so it becomes possible to prevent the extension of data writing time and incorrect writing. In addition, the diffusing distance in the transverse direction right under the FG can be made shorter than before, so that a memory cell is microminiaturized. COPYRIGHT: (C)1982,JPO&Japio

Inventors

• 👤 Hiroshi Iwahashi
• 👤 Masamichi Asano
• 👤 Kuniyoshi Yoshikawa
• 👤 Masaharu Mito

Bibliographic Details