Semiconductor memory cell device with thick insulative layer

Claim 2

A semiconductor integrated circuit device comprising: word lines which are made of a double-layer film comprising a first film of polycrystalline silicon and a second film of a silicide formed as a compound of silicon and a refractory metal and which extend in a row direction over a semiconductor substrate; data lines which extend in a column direction over said semiconductor substrate and two of which constitute one set of complementary data lines, each set of complementary data lines being connected to an identical memory cell; a plurality of memory cells each of which comprises cross-coupled first and second MISFETs, first and second switching MISFETs being connected between said first and second MISFETs and said complementary data lines and having their gate electrodes connected to said word lines, said first and second MISFETs and said first and second switching MISFETs each comprising source and drain regions in said semiconductor substrate, and a gate electrode on a first insulation film on said semiconductor substrate; and first wiring lines which are formed on a second insulation film on said semiconductor substrate, which serve to supply a ground potential to said memory cells, and which are made of the same layers as those of said word lines, wherein a thickness of said second insulation film is thicker than a thickness of said first insulation film.

Claim 3

A semiconductor integrated circuit device according to claim 1, wherein one of said source or drain of each of said first and second MISFETs is connected to said first wiring lines through via contact holes.

Claim 4

A semiconductor integrated circuit device according to claim 2, wherein said first and second MISFETs are n-channel MISFETs.

Claim 5

A semiconductor integrated circuit device according to claim 2, further comprising: load elements which are respectively coupled to said first and second MISFETs; and a second wiring which serves to supply a power source potential to said load elements and which is formed over said first wiring with a third insulation film intervening therebetween.

Claim 6

A semiconductor integrated circuit device according to claim 4, wherein said word line is made of a layer which contains a refractory metal, and wherein said load elements and said second wiring are made of polycrystalline silicon and are unitarily formed, said first, second and third insulation films being made of silicon oxide films.

Claim 7

A semiconductor integrated circuit device according to claim 1, wherein said first wiring lines extend substantially in the same direction as that of said word lines.

Claim 8

A semiconductor integrated circuit device according to claim 2, wherein said refractory metal is molybdenum.

Claim 9

A semiconductor integrated circuit device according to claim 2, wherein said refractory metal is tantalum.

Claim 10

A semiconductor integrated circuit device according to claim 2, wherein said refractory metal is titanium.

Claim 11

A semiconductor integrated circuit device according to claim 2, wherein said refractory metal is tungsten.

Claim 12

A semiconductor integrated circuit device according to claim 2, wherein each of said word lines is made of silicide film.

Claim 13

A semiconductor integrated circuit device comprising: word lines which are made of a double-layer film comprising a first film of polycrystalline silicon and a second film of a silicide formed as a compound of silicon and a refractory metal and which extend in a row direction over a semiconductor substrate; data lines which extend in a column direction over said semiconductor substrate and two of which constitute one set of complementary data lines, each set of complementary data lines being connected to an identical memory cell; a plurality of memory cells each of which comprises cross-coupled first and second MISFETs, first and second switching MISFETs being connected between said first and second MISFETs and said complementary data lines and having their gate electrodes connected to said word lines, said first and second MISFETs and said first and second switching MISFETs each comprising source and drain regions in said semiconductor substrate, and a gate electrode on a first insulation film on said semiconductor substrate; first wiring lines which are formed on a second insulation film on said semiconductor substrate, which serve to supply a ground potential to said memory cells, which are made of the same layers as those of said word lines, wherein a thickness of said second insulation film is thicker than a thickness of said first insulation film; load elements which are respectively coupled to said first and second MISFETs; and a second wiring line which serves to supply a first fixed potential to said load elements and which is formed over said first wiring with a third insulation film intervening therebetween.

Claim 14

A semiconductor integrated circuit device comprising: word lines which are made of a double-layer film comprising a first film of polycrystalline silicon and a second film of a silicide formed as a compound of silicon and a refractory metal and which extend in a row direction over a semiconductor substrate; data lines which extend in a column direction over said semiconductor substrate and two of which constitute one set of complementary data lines, each set of complementary data lines being connected to an identical memory cell; a plurality of memory cells each of which comprises cross-coupled first and second MISFETs, first and second switching MISFETs being connected between said first and second MISFETs and said complementary data lines and having their gate electrodes connected to said word lines, said first and second MISFETs and said first and second switching MISFETs each comprising source and drain regions in said semiconductor substrate, and a gate electrode on a first insulation film on said semiconductor substrate; first wiring lines which are formed on a second insulation film on said semiconductor substrate, which serve to supply a ground potential to said memory cells, which are made of the same layers as those of said word lines, wherein a thickness of said second insulation film is thicker than a thickness of said first insulation film; load elements which are respectively coupled to said first and second MISFETs; and a second wiring line which serves to supply a first fixed potential to said load elements and which is formed over said first wiring with a third insulation film intervening therebetween.

Claim 15

A semiconductor integrated circuit device according to claim 12, wherein said first and second MISFETs are n-channel MISFETs.

Claim 16

A semiconductor integrated circuit device according to claim 12, wherein said load elements are made of the same layers as those of said second wiring lines and are formed with said second wiring lines integrally.

Claim 17

A semiconductor integrated circuit device according to claim 12, wherein said load elements and said second wiring are made of polycrystalline silicon and are unitarily formed and wherein said first, second and third insulation films are made of silicon oxide films.

Claim 18

A semiconductor integrated circuit device according to claim 2, wherein said gate electrodes of said first and second MISFETs are made of the same layer as that of said word line, and one of said source and drain regions of each of said first and second MISFETs connected with said first wiring is formed longer than the other in a direction in which said gate electrode of said each MISFET extends.

Claim 19

A semiconductor integrated circuit device according to claim 12, wherein said first wiring lines extend substantially in the same direction as that of said word lines.