EP0088912A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Subthreshold load element for static ram cell
Assignee: Texas Instruments Inc
•
Filing: 1983-02-22
•
Granted: —
•
Expires: 2003-02-22
Abstract
Abstract A transistor operated in the subthreshold regime, e.g., a thick field parasitic FET, is utilized as a load element to maintain the state of a static RAM cell. The RAM cell is constructed with minimum spacing between devices to insure that the subthreshold current of the parasitic FET is sufficient to hold the memory state of the cell. This provides a useful purpose for a device characteristic (subthreshold leakage) that previously caused a problem in the increased isolation requirements; and additionally provides a major density improvement in SRAM cells.
Inventors
- 👤 Pallab K. Chatterjee
- 👤 Ashwin H. Shah
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-31 12:34
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/412; H; H10; H10B; H10B10/00; H10B10/12; H10D; H10D84/00; H10D84/80; H10D84/82; H10D84/83
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
57 words
A low power static random access memory cell, comprising: (a) cross-coupled drivers for providing regenerative feedback; (b) access means for electrically coupling said drivers to a random access memory array; and (c) field-effect transistor load for supplying holding current to said drivers; characterized in that said transistor load is connected to operate in the subthreshold regime thereof.
Claim 2
Dependent Claim
57 words
A low power static random access memory cell, comprising: (a) cross-coupled drivers for providing regenerative feedback; (b) access means for electrically coupling said drivers to a random access memory array; and (c) field-effect transistor load for supplying holding current to said drivers; characterized in that said transistor load is connected to operate in the subthreshold regime thereof.
Claim 3
Dependent Claim
20 words
A memory cell as set forth in Claim 1, wherein said transistor load is a thick field parasitic FET device.
Claim 4
Dependent Claim
22 words
A memory cell as set forth in Claim 1, wherein said drivers and said access means comprise enhancement mode field effect transistors.
Claim 5
Dependent Claim
32 words
A memory cell as set forth in Claim 3, wherein said transistor load comprises enhancement threshold field effect transistors having a threshold voltage lower than said driver means and said access means.
Claim 6
Dependent Claim
35 words
A memory cell as set forth in Claim 1, wherein said load means includes means for providing sufficient subthreshold load current to hold said driver means in a bistable state when in the store mode.
Claim 7
Dependent Claim
28 words
A memory cell as set forth in Claim 7, wherein said natural load means includes means for substantially reducing the short channel body effect of said transistor load.
Claim 8
Dependent Claim
25 words
A cell as set forth in Claim 4, wherein at least one of said enhancement threshold field effect transistors comprises a deep source/drain diode junction.
Claim 9
Dependent Claim
27 words
A cell as set forth in Claim 4, wherein at least one of said enhancement threshold field effect transistors comprises a deep level donor ion implanted impurity.
Claim 10
Dependent Claim
14 words
The cell of Claim l, wherein said transistor load comprises a natural load element.
Claim 11
Dependent Claim
12 words
A RAM array comprising a plurality of cells as in Claim 1.
Claim 12
Dependent Claim
25 words
A memory cell as in Claim 1, wherein the channel length of said parasitic FET load element is selected to achieve a desired load current.
Claim 13
Dependent Claim
12 words
A memory cell as in Claim 1, having a P-well CMOS configuration.
Claim 14
Dependent Claim
28 words
A load element for semiconductor integrated circuit, comprising a thick-field parasitic FET device, said device having a short channel length for establishment of a predetermined device current level.
Claim 15
Dependent Claim
28 words
A load element for semiconductor integrated circuit, comprising a thick-field parasitic FET device, said device having a short channel length for establishment of a predetermined device current level.
Claim 16
Dependent Claim
30 words
The load element of Claim 13, said device being defined by spacing of moat regions of natural devices such that current flows at a level usable for a high-impedance load.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.