Data processing system and method for performing dynamic bus termination

Claim 2

A data processing system having a communication device, the communication device being an integrated circuit having a plurality of external pins, the plurality of external pins being coupled to receive data from external to the communication device and transmit data external to the communication device, the communication device comprising: circuitry for signal termination having a plurality of first input/output terminals coupled to the plurality of external pins via a plurality of data lines, the circuitry for signal termination having a second input/output terminal for providing data to or receiving data from internal to the communication device, the circuitry for signal termination having an input for receiving an enable signal from either internal or external to the communication device and having a termination component, the enable signal allowing the circuitry for signal termination to couple the termination component to the plurality of external pins when the enable signal is asserted and decoupling the termination component from the plurality of external pins when the enable signal is deasserted.

Claim 3

The data processing system of claim 1 wherein the circuitry for signal termination reduces signal reflection of a voltage signal input from the plurality of external pins when the enable signal is asserted.

Claim 4

The data processing system of claim 1 further comprising: a multi-bit bi-directional bus coupled to the plurality of external pins for communicating either address or data information within the data processing system.

Claim 5

The data processing system of claim 3 wherein the data bus is coupled to a plurality of communication devices, the plurality of communication devices including said communication device.

Claim 6

The data processing system of claim 1 wherein the enable signal is a function of a first control signal internal to the communication device and a second control signal internal to the device, the first control signal being asserted by the communication device if the communication device is functioning as a bus master and being deasserted if the communication device is functioning as a bus slave, the second control signal being in a first logic state if a read operation is occurring through the plurality of external pins and being in a second logic state if a write operation is occurring through the plurality of external pins.

Claim 7

The data processing system of claim 1 wherein a bi-directional internal bus couples the circuitry for terminating with a data unit internal to the communication device.

Claim 8

The data processing system of claim 1 wherein a bi-directional internal bus couples the circuitry for terminating with a data unit internal to the communication device wherein the data unit is a device selected from a group consisting of: a memory array containing a plurality of memories, or a central processing unit (CPU) of a data processor.

Claim 9

The data processing system of claim 1 wherein the termination component is selected from a group consisting of: a resistive device, a diode, a capacitor, a voltage source, a current source, an inductor, a transistor, and a circuit comprising one or more of the above-listed elements.

Claim 10

A data processor within an integrated circuit package comprising: an execution unit internal to the data processor; a plurality of external pins connected to the integrated circuit package, the plurality of external pins used to bidirectionally communicate logic bits to and from the data processor via an external bus; a plurality of bus termination circuits, one bus termination circuit being coupled to one external pin of the plurality of external pins wherein each external pin is coupled to at least one bus termination circuit, the plurality of bus termination circuits providing data to or receiving data from the execution unit, each bus termination circuit in the plurality of bus termination circuits having an input for receiving a control signal; and a conductor coupled to each input of each of the bus termination circuits in the plurality of bus termination circuits, the conductor providing the control signal wherein the control signal, when asserted, allows each bus termination circuit in the plurality of bus termination circuits to couple at least one circuit component to the bus to reduce signal reflection on the bus, the control signal, when deasserted, allows each bus termination circuit in the plurality of bus termination circuits to decouple at least one circuit component from the bus.

Claim 11

A data processor within an integrated circuit package comprising: an execution unit internal to the data processor; a plurality of external pins connected to the integrated circuit package, the plurality of external pins used to bidirectionally communicate logic bits to and from the data processor via an external bus; a plurality of bus termination circuits, one bus termination circuit being coupled to one external pin of the plurality of external pins wherein each external pin is coupled to at least one bus termination circuit, the plurality of bus termination circuits providing data to or receiving data from the execution unit, each bus termination circuit in the plurality of bus termination circuits having an input for receiving a control signal; and a conductor coupled to each input of each of the bus termination circuits in the plurality of bus termination circuits, the conductor providing the control signal wherein the control signal, when asserted, allows each bus termination circuit in the plurality of bus termination circuits to couple at least one circuit component to the bus to reduce signal reflection on the bus, the control signal, when deasserted, allows each bus termination circuit in the plurality of bus termination circuits to decouple at least one circuit component from the bus.

Claim 12

The data processor of claim 9 wherein the at least one circuit component is a circuit component selected from a group consisting of: a capacitor, a diode, a resistor, a transistor, a voltage source, a current source, an electrical short circuit, and an inductor.

Claim 13

The data processor of claim 9 wherein the at least one circuit component is a plurality of first resistive devices wherein one first resistive device in the plurality of first resistive devices is coupled from each external pin in the plurality of external pins to a ground potential node.

Claim 14

The data processor of claim 9 wherein the at least one circuit component is a plurality of first resistive devices wherein one first resistive device in the plurality of first resistive devices is coupled from each external pin in the plurality of external pins to a power supply potential node.

Claim 15

The data processor of claim 9 wherein the at least one circuit component is a first plurality of resistive devices wherein one resistive device in the first plurality of resistive devices is coupled from each external pin in the plurality of external pins to a ground potential node and a second plurality of resistive devices wherein one resistive device in the second plurality of resistive devices is coupled from each external pin in the plurality of external pins to a power supply potential node wherein the power supply potential node is connected to receive a voltage greater than a voltage received by the ground potential node.

Claim 16

A data processor comprising: an execution unit internal to the data processor; a plurality of external pins used to bidirectionally communicate logic bits to and from the data processor via an external bus; a plurality of bus termination circuits, one bus termination circuit coupled to each external pin in the plurality of external pins, the plurality of bus termination circuits providing data to or receiving data from the execution unit, each bus termination circuit in the plurality of bus termination circuits having an input for receiving a control signal; and a conductor coupled to each input of each of the bus termination circuits in the plurality of bus termination circuits, the conductor providing the control signal wherein the control signal allows each bus termination circuit in the plurality of bus termination circuits to selectively reduce signal reflection in the external bus.

Claim 17

A data processor comprising: an execution unit internal to the data processor; a plurality of external pins used to bidirectionally communicate logic bits to and from the data processor via an external bus; a plurality of bus termination circuits, one bus termination circuit coupled to each external pin in the plurality of external pins, the plurality of bus termination circuits providing data to or receiving data from the execution unit, each bus termination circuit in the plurality of bus termination circuits having an input for receiving a control signal; and a conductor coupled to each input of each of the bus termination circuits in the plurality of bus termination circuits, the conductor providing the control signal wherein the control signal allows each bus termination circuit in the plurality of bus termination circuits to selectively reduce signal reflection in the external bus.

Claim 18

The data processor of claim 14 wherein a circuit component is connected to the bus only when the control signal is asserted to reduce signal reflection of an incoming voltage transmission from the bus.

Claim 19

A data processing system comprising: a master device having a dynamic bus termination circuit, the dynamic bus termination circuit being enabled when the master device is receiving data and disabled when the master device is sending data, the dynamic bus termination circuit of the master device reducing signal reflection of the data when the master device is receiving data; a bus coupled to the master device; and a slave device coupled to the bus, the slave device having a dynamic bus termination circuit, the dynamic bus termination circuit of the slave device being enabled when the slave device is receiving data from the master device and being disabled when the slave device is sending data to the master device, the dynamic bus termination circuit of the slave device reducing signal reflection of the data when the slave device is receiving data.

Claim 20

A data processing system comprising: a master device having a dynamic bus termination circuit, the dynamic bus termination circuit being enabled when the master device is receiving data and disabled when the master device is sending data, the dynamic bus termination circuit of the master device reducing signal reflection of the data when the master device is receiving data; a bus coupled to the master device; and a slave device coupled to the bus, the slave device having a dynamic bus termination circuit, the dynamic bus termination circuit of the slave device being enabled when the slave device is receiving data from the master device and being disabled when the slave device is sending data to the master device, the dynamic bus termination circuit of the slave device reducing signal reflection of the data when the slave device is receiving data.

Claim 23

The method of claim 17 wherein the step of enabling the circuitry comprises: enabling the termination circuitry in response to a first control signal within the data processor which is used to identify whether the data processor is a slave device or a master device and at least one second control signal within the data processor which is used to determine whether the bus is performing a read operation or a write operation.

Claim 26

The method of claim 19 wherein the steps (b) and (c) further comprise: enabling and disabling the termination circuitry based upon a control signal which indicates whether the device is a master device or a slave device.

Claim 27

The method of claim 19 wherein the step (b) further comprise: enabling the termination circuitry only for a brief time period wherein incoming data voltages are transitioning significantly within the brief period of time.

Claim 28

An integrated circuit having a terminal for communicating parallel binary data, the integrated circuit comprising: a data unit for storing and manipulating data within the integrated circuit; dynamic termination circuitry coupled between the data unit and the terminal for communicating parallel binary data, the dynamic termination circuitry having N physically separated termination circuits, where N is a finite positive integer greater than zero, each of the N physically separated termination circuits having at least one device wherein each at least one device: (1) provides an on/off switching capability respectively to each of the N physically separated termination circuits; and (2) is selectively used to change the impedance of the terminal for properly receiving the parallel binary data that is coming into the integrated circuit from external to the integrated circuit.

Claim 29

An integrated circuit having a terminal for communicating parallel binary data, the integrated circuit comprising: a data unit for storing and manipulating data within the integrated circuit; dynamic termination circuitry coupled between the data unit and the terminal for communicating parallel binary data, the dynamic termination circuitry having N physically separated termination circuits, where N is a finite positive integer greater than zero, each of the N physically separated termination circuits having at least one device wherein each at least one device: (1) provides an on/off switching capability respectively to each of the N physically separated termination circuits; and (2) is selectively used to change the impedance of the terminal for properly receiving the parallel binary data that is coming into the integrated circuit from external to the integrated circuit.

Claim 30

The integrated circuit of claim 22 wherein each of the N physically separated termination circuits are enabled via different enable signals.

Claim 31

The integrated circuit of claim 22 wherein the N physically separated termination circuits are connected in an interconnection scheme selected from the group consisting of: a parallel connection, a serial connection, a partially parallel connection, a partially serial connection, and a part-serial and part-parallel connection.

Claim 32

The integrated circuit of claim 22 wherein the N physically separated termination circuits are only enabled one at a time.

Claim 33

The integrated circuit of claim 22 wherein each of the N physically separated termination circuits are enabled at any time to provide one of a number of different termination circuit combinations wherein the different circuit combinations are equal a number selected within the range of two to 2 N different termination circuit combinations, the one of a number of different termination circuit combinations being coupled to the terminal for communicating the parallel binary data.

Claim 34

The integrated circuit of claim 22 wherein the impedance is selected via the at least one device to reduce signal reflection when receiving the data from the external to the integrated circuit via the terminal, the impedance being changed via the at least one device to another impedance when sending data external to the integrated circuit via the terminal.

Claim 37

A processor comprising: a CPU having a plurality of external terminals where the CPU is capable of being placed into a bus master mode of operation or a bus slave mode of operation, when in the bus master mode of operation the CPU has control of an external bus coupled to the plurality of terminals and when in a bus slave mode of operation the external bus is being controlled by a device other than the CPU; and circuitry coupled between the CPU and the external terminals for providing a selectable impedance to the plurality of external terminals in response to at least one control signal internal to the CPU, the selectable impedance being applied to the plurality of terminals: (1) when the CPU is in the bus master mode of operation and one of the at least one control signals indicates a read operation is being performed through the plurality of external terminals; and (2) when the CPU is in the bus slave mode of operation and one of the at least one control signals indicates a write operation is being performed through the plurality of external terminals.

Claim 38

A processor comprising: a CPU having a plurality of external terminals where the CPU is capable of being placed into a bus master mode of operation or a bus slave mode of operation, when in the bus master mode of operation the CPU has control of an external bus coupled to the plurality of terminals and when in a bus slave mode of operation the external bus is being controlled by a device other than the CPU; and circuitry coupled between the CPU and the external terminals for providing a selectable impedance to the plurality of external terminals in response to at least one control signal internal to the CPU, the selectable impedance being applied to the plurality of terminals: (1) when the CPU is in the bus master mode of operation and one of the at least one control signals indicates a read operation is being performed through the plurality of external terminals; and (2) when the CPU is in the bus slave mode of operation and one of the at least one control signals indicates a write operation is being performed through the plurality of external terminals.