US5294845A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Data processor having an output terminal with selectable output impedances
Assignee: NXP USA Inc
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Filing: 1992-08-17
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Granted: 1994-03-15
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Expires: 2012-08-17
Abstract
Abstract A data processor has at least one output terminal which a user of the data processor can vary the output impedance thereof depending upon the application environment of the data processor. A first output buffer of an output buffer stage has a predetermined output impedance and is coupled between an input of the stage and the output terminal. The first output buffer provides a first output terminal impedance. A second output buffer having a lower output impedance than the first output buffer may be selectively coupled in parallel to the first output buffer to reduce the output impedance of the output terminal. The coupling of the output buffers is controlled by a user of the data processor who provides a control input for selecting one of a plurality of predetermined output terminal impedance values.
Inventors
- 👤 Steven C. McMahan
- 👤 Kenneth C. Scheuer
- 👤 William B. Ledbetter, Jr.
- 👤 Michael G. Gallup
- 👤 James G. Gay
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 05:40
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/0175; H03K19/017581; H03K19/0005
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
179 words
In an integrated circuit, a circuit having an output terminal, comprising: a storage device having an input for receiving a user controllable signal having a value which is controlled and may be varied by a user of the integrated circuit only during a reset mode of operation of the integrated circuit, the user controllable signal being varied in response to an impedance selection input being asserted by the user at an input pin of the integrated circuit, the storage device providing a control signal; and a plurality of output buffers, each output buffer having a predetermined buffer output impedance, an input coupled to a buffer information input terminal of the circuit, and an output directly connected to a common node which is coupled to the output terminal of the circuit, at least one of the plurality of output buffers being electrically coupled between the information input terminal and the output terminal in response to the control signal, the user being able to select predetermined discrete, output impedances of the circuit by controlling the value of the impedance selection input.
Claim 2
Dependent Claim
179 words
In an integrated circuit, a circuit having an output terminal, comprising: a storage device having an input for receiving a user controllable signal having a value which is controlled and may be varied by a user of the integrated circuit only during a reset mode of operation of the integrated circuit, the user controllable signal being varied in response to an impedance selection input being asserted by the user at an input pin of the integrated circuit, the storage device providing a control signal; and a plurality of output buffers, each output buffer having a predetermined buffer output impedance, an input coupled to a buffer information input terminal of the circuit, and an output directly connected to a common node which is coupled to the output terminal of the circuit, at least one of the plurality of output buffers being electrically coupled between the information input terminal and the output terminal in response to the control signal, the user being able to select predetermined discrete, output impedances of the circuit by controlling the value of the impedance selection input.
Claim 3
Dependent Claim
15 words
The circuit of claim 1 wherein the plurality of output buffers comprises two output buffers.
Claim 4
Dependent Claim
13 words
The circuit of claim 1 wherein the storage device is a storage register.
Claim 5
Dependent Claim
64 words
The circuit of claim 1 wherein the control signal which couples the at least one of the plurality of output buffers between the buffer information input terminal and the output terminal is a single control signal having a plurality of bits, and one or more predetermined bit of the plurality of bits is used to control each output buffer which is being user controlled.
Claim 6
Dependent Claim
39 words
The circuit of claim 1 wherein the control signal which couples the at least one of the plurality of output buffers between the buffer information input terminal and the output terminal is a distinct signal for each output buffer.
Claim 7
Dependent Claim
189 words
In an integrated circuit, a circuit comprising: storage means having an input and an output, the storage means receiving a user controlled select input signal provided by a user of the integrated circuit, the storage means also providing a control signal; and a plurality of output buffers, each of the plurality of output buffers having a predetermined buffer output impedance and being coupled between a buffer information input terminal of the circuit and an output terminal of the circuit, at least one of the plurality of output buffers receiving the control signal provided by the storage means, the control signal having a value which is controlled and may be varied by the user of the circuit, the user being able only during a reset mode of the integrated circuit to select one of a plurality of discrete, output impedances for the circuit by controlling the value of the control signal by inputting the select input signal to an input pin of the integrated circuit, the user not being able to change the selected one of the output impedances when the integrated circuit is in any other mode of operation.
Claim 8
Dependent Claim
189 words
In an integrated circuit, a circuit comprising: storage means having an input and an output, the storage means receiving a user controlled select input signal provided by a user of the integrated circuit, the storage means also providing a control signal; and a plurality of output buffers, each of the plurality of output buffers having a predetermined buffer output impedance and being coupled between a buffer information input terminal of the circuit and an output terminal of the circuit, at least one of the plurality of output buffers receiving the control signal provided by the storage means, the control signal having a value which is controlled and may be varied by the user of the circuit, the user being able only during a reset mode of the integrated circuit to select one of a plurality of discrete, output impedances for the circuit by controlling the value of the control signal by inputting the select input signal to an input pin of the integrated circuit, the user not being able to change the selected one of the output impedances when the integrated circuit is in any other mode of operation.
Claim 9
Dependent Claim
15 words
The circuit of claim 6 wherein the plurality of output buffers comprises two output buffers.
Claim 10
Dependent Claim
35 words
The circuit of claim 6 wherein the control signal provided by the storage means biases at least a first of the output buffers with same logic values as a second of the output buffer circuits.
Claim 11
Dependent Claim
13 words
The circuit of claim 8 wherein the storage means is a storage register.
Claim 12
Dependent Claim
42 words
The circuit of claim 6 wherein a first of the plurality of output buffers is controlled by a voltage reference terminal which permanently connects the first of the plurality of output buffers between the buffer information input terminal and the output terminal.
Claim 13
Dependent Claim
26 words
The circuit of claim 8 wherein the input pin of the integrated circuit is used for another function when the integrated circuit is not being reset.
Claim 14
Independent Claim
219 words
A method for controlling output impedance of a circuit in an integrated circuit, comprising the steps of: providing a plurality of output buffers, each output buffer having a predetermined buffer output impedance; connecting each output buffer to an information input terminal of the circuit and directly connecting each output buffer to a common node which is coupled to an output terminal of the circuit; providing a storage device for receiving a user controllable signal having a value which is controlled by a user of the integrated circuit and which may be varied by a user only during a reset mode of operation of the integrated circuit; providing each output buffer with a control terminal for receiving a control signal; and allowing the user of the circuit to select a value of the control signal to permit the user of the circuit to select one of a plurality of predetermined, discrete output impedance values for the output terminal of the circuit, the user being able only during the reset mode of operation of the integrated circuit to change an output impedance of the output terminal from a first substantially constant impedance to a second substantially constant impedance by modifying the value of the control signal in response to providing a select signal at an input pin of the integrated circuit.
Claim 15
Independent Claim
219 words
A method for controlling output impedance of a circuit in an integrated circuit, comprising the steps of: providing a plurality of output buffers, each output buffer having a predetermined buffer output impedance; connecting each output buffer to an information input terminal of the circuit and directly connecting each output buffer to a common node which is coupled to an output terminal of the circuit; providing a storage device for receiving a user controllable signal having a value which is controlled by a user of the integrated circuit and which may be varied by a user only during a reset mode of operation of the integrated circuit; providing each output buffer with a control terminal for receiving a control signal; and allowing the user of the circuit to select a value of the control signal to permit the user of the circuit to select one of a plurality of predetermined, discrete output impedance values for the output terminal of the circuit, the user being able only during the reset mode of operation of the integrated circuit to change an output impedance of the output terminal from a first substantially constant impedance to a second substantially constant impedance by modifying the value of the control signal in response to providing a select signal at an input pin of the integrated circuit.
Claim 16
Dependent Claim
46 words
The method of claim 12 further comprising the step of: providing an additional output buffer having a first input terminal connected to a reference voltage terminal, a second input terminal connected to the control signal, and an output connected to the output terminal of the circuit.
Claim 17
Dependent Claim
19 words
The method of claim 12 wherein the step of providing a storage device further comprises providing a storage register.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-03-14 | 1997-09-13 | 1998-03-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-03-14 | 2001-09-13 | 2002-03-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-03-14 | 2005-09-13 | 2006-03-15 | $7700.00 | Window Closed / Lapsed |