Programmable mode select by reset

Claim 2

An integrated circuit microprocessor comprising: an input/output terminal, a reset terminal, an input storage element for storing digital information input to the microprocessor, an output storage element for storing digital information to be output from the microprocessor, reset means for receiving a reset signal coupled to the reset terminal, and for resetting and initializing the microprocessor to perform a predetermined operation, in response to the reset signal changing from a first predetermined voltage level to a second predetermined voltage level, input/output means coupled to the reset means and to the output storage element, for selectively coupling the output storage element to the input/output terminal in response to at least one operation of the microprocessor, but only when the reset signal is at the second voltage level, and voltage level detection means coupled to the reset means and to the input storage element, for selectively coupling the input storage element to the input/output terminal when the reset signal is at the first voltage level, and for uncoupling the input storage element from the input/output terminal when the reset signal thereafter changes to a predetermined voltage level intermediate the first and second voltage levels.

Claim 3

The microprocessor as recited in claim 1 wherein the input storage element comprises a latch circuit.

Claim 4

The microprocessor as recited in claim 2 wherein the latch circuit is responsive to a digital signal coupled thereto from the input/output terminal by the voltage level detection means only when the reset signal is at the first voltage level.

Claim 5

The microprocessor as recited in claim 1 further including mode selection circuitry responsive to the contents of the input storage element for selecting the operating mode of the microprocessor.

Claim 6

A circuit for use in an integrated circuit microprocessor for storing a mode selection signal representing a particular one of a plurality of possible operating modes for the microprocessor, the circuit comprising: a first terminal for receiving a reset signal; reset means coupled to the first terminal, for resetting and initializing the microprocessor to perform a predetermined operation in response to the reset signal changing from a first predetermined voltage level to a second predetermined voltage level; a second terminal for receiving the mode selection signal; a storage circuit for storing the mode selection signal upon the mode selection signal being coupled thereto; voltage level detection means coupled to the first terminal, for generating a control signal having a first state when the reset signal is at a first predetermined voltage level and having a second state when the reset signal thereafter changes to a third predetermined voltage level intermediate the first and second predetermined voltage levels; and coupling means coupled between the storage circuit and the second terminal and responsive to the control signal, for coupling the second terminal to the storage circuit when the control signal is in the first state, and for uncoupling the second terminal from the storage circuit when the control signal is in the second state, whereby the mode selection signal received by the second terminal when the reset signal is at the first voltage level is selectively coupled to, and stored by, the storage circuit.

Claim 7

A circuit for use in an integrated circuit microprocessor for storing a mode selection signal representing a particular one of a plurality of possible operating modes for the microprocessor, the circuit comprising: a first terminal for receiving a reset signal; reset means coupled to the first terminal, for resetting and initializing the microprocessor to perform a predetermined operation in response to the reset signal changing from a first predetermined voltage level to a second predetermined voltage level; a second terminal for receiving the mode selection signal; a storage circuit for storing the mode selection signal upon the mode selection signal being coupled thereto; voltage level detection means coupled to the first terminal, for generating a control signal having a first state when the reset signal is at a first predetermined voltage level and having a second state when the reset signal thereafter changes to a third predetermined voltage level intermediate the first and second predetermined voltage levels; and coupling means coupled between the storage circuit and the second terminal and responsive to the control signal, for coupling the second terminal to the storage circuit when the control signal is in the first state, and for uncoupling the second terminal from the storage circuit when the control signal is in the second state, whereby the mode selection signal received by the second terminal when the reset signal is at the first voltage level is selectively coupled to, and stored by, the storage circuit.

Claim 8

The circuit as recited in claim 5 wherein the voltage level detection means comprises: reference voltage means for providing a reference voltage at the predetermined voltage level intermediate the first and second voltages, and a differential amplifier including first and second MOSFET devices having the source terminals thereof coupled together, the gate terminal of the first MOSFET device coupled to the first terminal, and the gate terminal of the second MOSFET device coupled to the reference voltage means.

Claim 9

An integrated circuit microprocessor comprising: a reset terminal; a first terminal; reset means coupled to the reset terminal, for resetting and initializing the microprocessor to perform a predetermined operation in response to a reset signal applied to the reset terminal changing from a first predetermined voltage to a second predetermined voltage; storage means for storing digital data upon the data being coupled thereto; voltage level detection means coupled to the reset means, for generating a control signal having a first state when the reset signal is at the first predetermined voltage level and having a second state when the reset signal thereafter changes to a third predetermined voltage level intermediate the first and second predetermined voltage levels; first coupling means coupled between the storage means and the first terminal, for selectively coupling the storage element to the first terminal in response to at least one operation of the microprocessor but only when the reset signal is at the second voltage level; and second coupling means coupled between the storage means and the first terminal and responsive to the control signal, for coupling the first terminal to the storage means when the control signal is in the first state, and for uncoupling the first terminal from the storage means when the control signal is in the second state, whereby digital data received by the first terminal when the reset signal is at the first voltage level is selectively coupled to, and stored by, the storage means.

Claim 10

An integrated circuit microprocessor comprising: a reset terminal; a first terminal; reset means coupled to the reset terminal, for resetting and initializing the microprocessor to perform a predetermined operation in response to a reset signal applied to the reset terminal changing from a first predetermined voltage to a second predetermined voltage; storage means for storing digital data upon the data being coupled thereto; voltage level detection means coupled to the reset means, for generating a control signal having a first state when the reset signal is at the first predetermined voltage level and having a second state when the reset signal thereafter changes to a third predetermined voltage level intermediate the first and second predetermined voltage levels; first coupling means coupled between the storage means and the first terminal, for selectively coupling the storage element to the first terminal in response to at least one operation of the microprocessor but only when the reset signal is at the second voltage level; and second coupling means coupled between the storage means and the first terminal and responsive to the control signal, for coupling the first terminal to the storage means when the control signal is in the first state, and for uncoupling the first terminal from the storage means when the control signal is in the second state, whereby digital data received by the first terminal when the reset signal is at the first voltage level is selectively coupled to, and stored by, the storage means.

Claim 11

The microprocessor of claim 7 wherein the digital data stored by the storage means represents a particular one of a plurality of possible operating modes of the microprocessor, the microprocessor further including: mode select means coupled to the storage means, for selecting the particular one of the plurality of possible operating modes of the microprocessor represented by the stored digital data upon the resetting of the microprocessor by the reset means in response to the reset signal.

Claim 12

An integrated circuit microprocessor having a plurality of possible operating modes comprising: a reset terminal; a data terminal for receiving digital data representing a particular one of said plurality of operating modes; storage means for storing said digital data upon the data being coupled thereto; reset means coupled to the reset terminal, for resetting and initializing the microprocessor to perform a predetermined operation in the one of said possible operating modes represented by the data stored in the storage means, in response to a reset signal applied to the reset terminal changing from a first predetermined voltage to a second predetermined voltage; voltage level detection means coupled to the reset terminal, for generating a control signal having a first state when the reset signal is at the first predetermined voltage level and having a second state when the reset signal thereafter changes to a third predetermined voltage level intermediate the first and second predetermined voltage levels; and coupling means coupled between the storage means and the data terminal and responsive to the control signal, for coupling the data terminal to the storage means when the control signal is in the first state, and for uncoupling the data terminal from the storage means when the control signal is in the second state, whereby digital data received by the data terminal when the reset signal is at the first voltage level is selectively coupled to, and stored by, the storage means.

Claim 13

An integrated circuit microprocessor having a plurality of possible operating modes comprising: a reset terminal; a data terminal for receiving digital data representing a particular one of said plurality of operating modes; storage means for storing said digital data upon the data being coupled thereto; reset means coupled to the reset terminal, for resetting and initializing the microprocessor to perform a predetermined operation in the one of said possible operating modes represented by the data stored in the storage means, in response to a reset signal applied to the reset terminal changing from a first predetermined voltage to a second predetermined voltage; voltage level detection means coupled to the reset terminal, for generating a control signal having a first state when the reset signal is at the first predetermined voltage level and having a second state when the reset signal thereafter changes to a third predetermined voltage level intermediate the first and second predetermined voltage levels; and coupling means coupled between the storage means and the data terminal and responsive to the control signal, for coupling the data terminal to the storage means when the control signal is in the first state, and for uncoupling the data terminal from the storage means when the control signal is in the second state, whereby digital data received by the data terminal when the reset signal is at the first voltage level is selectively coupled to, and stored by, the storage means.