Output buffer tri-state noise reduction circuit

Claim 2

An output buffer circuit capable of switching from the off state to the on state, and from the on state to the off state, without generating significant noise, comprising: an MOS inverter circuit having a first node for connection to one terminal of a power supply and a second node for connection to the other power supply node, and having an input means for receiving an input signal and an output means for providing an output signal to an output transistor; a first MOS transistor of one polarity type and of either enhancement or depletion mode, having its source-drain circuit coupled in series with said first node of said MOS inverter circuit; a second MOS transistor of the opposite polarity type or mode from said first MOS transistor, having its source-drain circuit coupled in series with the said other node of said MOS inverter circuit; a means for supplying a first reference voltage to the gate of said first MOS transistor and for supplying a second reference voltage which is the mirror of said first reference voltage to the gate of said second MOS transistor, said reference voltages enabling said first and second MOS transistors to act like constant current sources which generate stable currents over normal variations in operating and processing conditions of the MOS transistors in the circuit, whereby the rise and fall times of said output signal from said inverter circuit are precisely controlled irrespective of normal changes in operating or processing conditions of the MOS transistors in the circuit, thereby reducing the noise when said output transistor connected to said output means is turned on or off.

Claim 3

An output buffer circuit capable of switching from the off state to the on state, and from the on state to the off state, without generating significant noise, comprising: an MOS inverter circuit having two MOS transistors, a first P-channel transistor and a second N-channel transistor, the source of the P-channel transistor being for connection to the positive terminal of a power supply and the source of the N-channel transistor being for connection to the other terminal of said power supply, and having an input means coupled to the gates of said two MOS transistors and an output means coupled to the drain terminals of said first and second MOS transistors, said output means being for connection to an output transistor; a third MOS transistor of one polarity type and one mode having its source-drain circuit coupled in series between the source of said first P-channel MOS transistor of said inverter circuit and said positive terminal of said power supply; a fourth MOS transistor opposite in either polarity type or mode from said first transistor, having its source-drain circuit coupled in series between the source of said second MOS transistor of said inverter circuit and said other terminal of said power supply; a means for supplying a first reference voltage to the gate of said third MOS transistor and for supplying a second reference voltage which is the mirror of said first reference voltage to the gate of said fourth MOS transistor, said reference voltages enabling said first and second MOS transistors to act like constant current sources which generate stable currents over normal variations in operating and processing conditions, whereby the rise and fall times of said output signal from said inverter are precisely controlled irrespective of normal changes in operating or processing conditions, thereby reducing noise when said output transistor connected to said output means is turned on or off.

Claim 4

An output buffer circuit capable of switching from the off state to the on state, and from the on state to the off state, without generating significant noise, comprising: an MOS inverter circuit having two MOS transistors, a first P-channel transistor and a second N-channel transistor, the source of the P-channel transistor being for connection to the positive terminal of a power supply and the source of the N-channel transistor being for connection to the other terminal of said power supply, and having an input means coupled to the gates of said two MOS transistors and an output means coupled to the drain terminals of said first and second MOS transistors, said output means being for connection to an output transistor; a third MOS transistor of one polarity type and one mode having its source-drain circuit coupled in series between the source of said first P-channel MOS transistor of said inverter circuit and said positive terminal of said power supply; a fourth MOS transistor opposite in either polarity type or mode from said first transistor, having its source-drain circuit coupled in series between the source of said second MOS transistor of said inverter circuit and said other terminal of said power supply; a means for supplying a first reference voltage to the gate of said third MOS transistor and for supplying a second reference voltage which is the mirror of said first reference voltage to the gate of said fourth MOS transistor, said reference voltages enabling said first and second MOS transistors to act like constant current sources which generate stable currents over normal variations in operating and processing conditions, whereby the rise and fall times of said output signal from said inverter are precisely controlled irrespective of normal changes in operating or processing conditions, thereby reducing noise when said output transistor connected to said output means is turned on or off.

Claim 5

The output buffer circuit of claim 2 further characterized by said means for supplying said second reference voltage including a current mirror circuit having as its input voltage said first reference voltage.

Claim 6

The output buffer circuit of claim 2 further characterized by said inverter being a CMOS circuit, said first MOS transistor being of one polarity type and said second MOS transistor being of the opposite polarity type.

Claim 7

The output buffer circuit of claim 4 further characterized by said third MOS transistor being of the same polarity type as said first MOS transistor and said fourth MOS transistor being of the same polarity type as said second MOS transistor.

Claim 8

The output buffer circuit of claim 1 further characterized by said output means of said inverter circuit being coupled to the gate of a fifth MOS pull down transistor, one of the source or drain of said fifth MOS transistor providing the output signal from said buffer circuit and the other of said source or drain terminals of said fifth MOS being coupled to a point of fixed potential.