High speed impedance sensitive switch driver

Claim 2

A high speed, impedance sensitive, amplifying switch driver comprising: an input terminal for selectively receiving a first input signal of a first voltage accompanied by a high impedance state and a second input signal of a second voltage accompanied by a low impedance state; an output terminal for presenting first and second high speed amplified switching signals corresponding to said input signals; an output stage including first and second semiconductor means each having a first load electrode connected to said output terminal for alternately, selectively producing said first and second switching signals; an intermediate switching stage including third and fourth semiconductor means each having a first load electrode connected in common to the control electrodes of said first and second semiconductor means, for alternately, selectively driving said first and second semiconductor means; an input stage including means for alternately, selectively biasing one of said third and fourth semiconductor means in a low conduction state and the other in a high conduction state in response to said first and second input signals, said means for biasing including voltage divider means having a first tap connected to the control electrode of said third semiconductor means and a second tap connected with the control electrode of said fourth semiconductor means, and seventh semiconductor means having its control electrode connected to said input terminal and with said first tap and its first load electrode connected to said second tap, said control electrode of said seventh semiconductor means being connected to said first tap through a resistor and said second tap being connected to said control electrode of said fourth semiconductor means through a capacitor.

Claim 3

A high speed, impedance sensitive amplifying switch driver circuit comprising: an output terminal and an output stage including first and second complementary transistors with their emitter electrodes connected together and to said output terminal and their collector electrodes connected one to a positive power supply terminal, the other to a negative power supply terminal; an intermediate stage including third and fourth complementary transistors operating in their linear regions and having their collector electrodes connected respectively to the base electrodes of said first and second transistors, each of said third and fourth transistors being alternately in a state of conducting more and conducting less, the one of said third and fourth transistors which is conducting more acting to dissipate the stray capacitance associated with each of those transistors; an input terminal and a first voltage divider including a first part having a first resistor in series between one power supply terminal and the emitter of said third transistor and a second resistor connected between said first resistor and the emitter of a fifth transistor and a second part having a third resistor connected in series between the other power supply terminal and the emitter of said fourth transistor and a fourth resistor connected between said third resistor and the emitter of a sixth transistor; said fifth and sixth transistors each have their base electrodes connected to said input terminal; and a first capacitor interconnected between said emitter of said third transistor and said emitter of said sixth transistor and a second capacitor interconnected between said emitter of said fourth transistor and said emitter of said fifth transistor.

Claim 4

A high speed, impedance sensitive amplifying switch driver circuit comprising: an output terminal and an output stage including first and second complementary transistors with their emitter electrodes connected together and to said output terminal and their collector electrodes connected one to a positive power supply terminal, the other to a negative power supply terminal; an intermediate stage including third and fourth complementary transistors operating in their linear regions and having their collector electrodes connected respectively to the base electrodes of said first and second transistors, each of said third and fourth transistors being alternately in a state of conducting more and conducting less, the one of said third and fourth transistors which is conducting more acting to dissipate the stray capacitance associated with each of those transistors; an input terminal and a first voltage divider including a first part having a first resistor in series between one power supply terminal and the emitter of said third transistor and a second resistor connected between said first resistor and the emitter of a fifth transistor and a second part having a third resistor connected in series between the other power supply terminal and the emitter of said fourth transistor and a fourth resistor connected between said third resistor and the emitter of a sixth transistor; said fifth and sixth transistors each have their base electrodes connected to said input terminal; and a first capacitor interconnected between said emitter of said third transistor and said emitter of said sixth transistor and a second capacitor interconnected between said emitter of said fourth transistor and said emitter of said fifth transistor.

Claim 5

The high speed, impedance sensitive amplifying switch driver circuit of claim 2 further including a second voltage divider network interconnected between said power supply terminals and having a first tap connected to the base electrode of said third transistor and a second tap connected to the basE electrode of said fourth transistor.

Claim 6

A high speed, impedance sensitive amplifying switch driver circuit comprising: an output terminal and an output stage including first and second complementary transistors with their emitter electrodes connected together and to said output terminal and their collector electrodes connected one to a positive power supply terminal, the other to a negative power supply terminal; an intermediate stage including third and fourth complementary transistors operating in their linear regions and having their collector electrodes connected to the base electrodes of said first and second transistors, respectively, each of said third and fourth transistors alternately in a state of conducting more and conducting less, the one of said third and fourth transistors which is conducting more acting to dissipate the stray capacitance associated with each of those transistors; and an input terminal and a first voltage divider network extending from one of the power supply terminals to said input terminal and having a first tap connected with the base electrode of said third transistor, said input terminal being coupled through said voltage divider network to said base electrode of said third transistor for varying the bias on said base electrode of said third transistor as a function of a change in impedance at said input terminal, the base electrode of said fourth transistor being connected through a bias resistor to the other power supply terminal and through a capacitor to the emitter of a buffer transistor having its collector connected to the said one power supply terminal and its base electrode directly connected to said input terminal, said circuit being connected in an open loop configuration in which said intermediate stage isolates said output stage from said input stage.

Claim 7

A high speed, impedance sensitive amplifying switch driver circuit comprising: an output terminal and an output stage including first and second complementary transistors with their emitter electrodes connected together and to said output terminal and their collector electrodes connected one to a positive power supply terminal, the other to a negative power supply terminal; an intermediate stage including third and fourth complementary transistors operating in their linear regions and having their collector electrodes connected to the base electrodes of said first and second transistors, respectively, each of said third and fourth transistors alternately in a state of conducting more and conducting less, the one of said third and fourth transistors which is conducting more acting to dissipate the stray capacitance associated with each of those transistors; and an input terminal and a first voltage divider network extending from one of the power supply terminals to said input terminal and having a first tap connected with the base electrode of said third transistor, said input terminal being coupled through said voltage divider network to said base electrode of said third transistor for varying the bias on said base electrode of said third transistor as a function of a change in impedance at said input terminal, the base electrode of said fourth transistor being connected through a bias resistor to the other power supply terminal and through a capacitor to the emitter of a buffer transistor having its collector connected to the said one power supply terminal and its base electrode directly connected to said input terminal, said circuit being connected in an open loop configuration in which said intermediate stage isolates said output stage from said input stage.