US5432103A
Expired / Lapsed
US
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Method of making semiconductor ROM cell programmed using source mask
Assignee: National Semiconductor Corp
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Filing: 1992-12-23
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Granted: 1995-07-11
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Expires: 2012-12-23
Abstract
Abstract ROM cell programmed ON has N+ source implant spaced a given distance from the gate with LDD bridging the gap between the N+ source and the N channel. ROM cell programmed OFF has P+ implanted into this gap so as to completely override the LDD in this gap. The P+ prevents the N channel from forming ohmic connection to the N+ source.
Inventors
- 👤 William E. Miller
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 19:57
CPC Classifications
H; H10; H10B; H10B20/00
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
123 words
A method for fabricating a ROM containing a plurality of ROM cells, the ROM cells formed of a substrate having a drain and a source of first conductivity type, a gate oxide layer formed on a surface of the substrate, and a polysilicon gate adjacent the drain and formed on the surface of the substrate, the method comprising the steps of: forming a mask over the surface of the substrate except over given regions of selected ROM cells to be programmed to an inactive state; and implanting material of a second conductivity type in the given regions to form an implant of the second conductivity type that is laterally bounded on both sides by regions of the source having the first conductivity type.
Claim 2
Independent Claim
123 words
A method for fabricating a ROM containing a plurality of ROM cells, the ROM cells formed of a substrate having a drain and a source of first conductivity type, a gate oxide layer formed on a surface of the substrate, and a polysilicon gate adjacent the drain and formed on the surface of the substrate, the method comprising the steps of: forming a mask over the surface of the substrate except over given regions of selected ROM cells to be programmed to an inactive state; and implanting material of a second conductivity type in the given regions to form an implant of the second conductivity type that is laterally bounded on both sides by regions of the source having the first conductivity type.
Claim 3
Dependent Claim
50 words
The method for fabricating a ROM of claim 1 further comprising the step of: forming a drain contact and a source contact; and wherein the step of forming a mask and the step of implanting material occur prior to the step of forming the drain contact and the source contact.
Claim 4
Dependent Claim
33 words
The method for fabricating a ROM of claim 2 wherein the step of implanting material comprises implanting the material of the second conductivity type to a concentration density of approximately 5×10 19 atoms/cm3.
Claim 5
Dependent Claim
18 words
The method for fabricating a ROM of claim 2 wherein the ROM is formed in a "T" layout.
Claim 6
Dependent Claim
51 words
The method for fabricating a ROM of claim 1 further comprising the step of: forming a drain contact and a source contact by metallization; and wherein the step of forming a mask and the step of implanting material occur after the step of forming the drain contact and the source contact.
Claim 7
Dependent Claim
33 words
The method for fabricating a ROM of claim 5 wherein the step of implanting material comprises implanting the material of the second conductivity type to a concentration density of approximately 5×10 17 atoms/cm3.
Claim 8
Dependent Claim
18 words
The method for fabricating a ROM of claim 5 wherein the ROM is formed in an "X" layout.
Claim 9
Dependent Claim
28 words
The method for fabricating a ROM of claim 1 wherein the step of implanting material of a second conductivity type comprises the step of implanting P type material.
Claim 10
Independent Claim
141 words
A method of ROM manufacture comprising the steps of: forming in a common substrate a plurality of transistors, each of said transistors including a source region and a drain region of a first conductivity type spaced apart a given distance wherein each of said source and drain regions includes a heavily doped main portion and a lightly doped portion and wherein said transistors further include a gate electrode overlying a surface of said substrate and adjacent said lightly doped portions; masking selected transistors according to a desired programming code; and subjecting said plurality of transistors to an implant of a second conductivity type to form an implant region of opposite conductivity type between said lightly doped portion of said source and said heavily doped main portion of said source, whereby said transistors having said implant are programmed to an inactive state.
Claim 11
Independent Claim
141 words
A method of ROM manufacture comprising the steps of: forming in a common substrate a plurality of transistors, each of said transistors including a source region and a drain region of a first conductivity type spaced apart a given distance wherein each of said source and drain regions includes a heavily doped main portion and a lightly doped portion and wherein said transistors further include a gate electrode overlying a surface of said substrate and adjacent said lightly doped portions; masking selected transistors according to a desired programming code; and subjecting said plurality of transistors to an implant of a second conductivity type to form an implant region of opposite conductivity type between said lightly doped portion of said source and said heavily doped main portion of said source, whereby said transistors having said implant are programmed to an inactive state.
Claim 12
Dependent Claim
24 words
The method of ROM manufacture of claim 9 wherein said step of masking selected transistors occurs prior to formation of drain and source contacts.
Claim 13
Dependent Claim
36 words
The method of ROM manufacture of claim 10 wherein said step of implanting material comprises the step of implanting material of the second conductivity type to a concentration density of approximately 5×10 19 atoms/cm 3 .
Claim 14
Dependent Claim
17 words
The method of ROM manufacture of claim 10 wherein the ROM is formed in a "T" layout.
Claim 15
Dependent Claim
23 words
The method of ROM manufacture of claim 9 wherein said step of masking selected transistors occurs after formation of drain and source contacts.
Claim 16
Dependent Claim
35 words
The method for fabricating a ROM of claim 13 wherein the step of implanting material comprises implanting the material of the second conductivity type to a concentration density of approximately 5×10 17 atoms/cm 3 .
Claim 17
Dependent Claim
18 words
The method for fabricating a ROM of claim 13 wherein the ROM is formed in an "X" layout.
Claim 18
Dependent Claim
28 words
The method for fabricating a ROM of claim 9 wherein the step of implanting material of a second conductivity type comprises the step of implanting P type material.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-07-10 | 1999-01-09 | 1999-07-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-07-10 | 2003-01-09 | 2003-07-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-07-10 | 2007-01-09 | 2007-07-11 | $7700.00 | Window Closed / Lapsed |