Semiconductor integrated circuit device with two variable delay lines in writing circuit control

Claim 2

A semiconductor integrated circuit device comprising: a write pulse generation circuit for generating a write pulse signal on the basis of a clock signal; and a memory circuit which has a writing operation designated in accordance with said write pulse signal; wherein said write pulse generation circuit includes: pulse width setting means including a plurality of first delay circuits connected in series for setting a pulse width of said write pulse signal; a first decoder circuit for selecting a predetermined delay circuit from said plurality of first delay circuits in accordance with a first control signal supplied from outside of said semiconductor integrated circuit device so that said pulse width setting means sets said pulse width of said write pulse signal; set-up time setting means including a plurality of second delay circuits connected in series for setting a set-up time of said write pulse signal; and a second decoder circuit for selecting a predetermined delay circuit from said plurality of second delay circuits in accordance with a second control signal supplied from outside of said semiconductor integrated circuit device so that said set-up time setting means sets said set-up time of said write pulse signal.

Claim 3

A semiconductor integrated circuit device according to claim 1, wherein said memory circuit is a static random access memory.

Claim 4

A semiconductor integrated circuit device according to claim 2, wherein said static random access memory includes a memory cell for storing data and a write circuit for writing predetermined data to said memory cell, and wherein said write pulse generation circuit outputs said write pulse signal to said write circuit.

Claim 5

A semiconductor integrated circuit device according to claim 3 further comprising external terminals, wherein said first and second control signals are supplied to said external terminals from outside of said semiconductor integrated circuit device.

Claim 6

A semiconductor integrated circuit device according to claim 4, wherein said first and second control signals are multi-bit pulse width and multi-bit set-up time select control signals, respectively.

Claim 7

A semiconductor integrated circuit device according to claim 5, wherein said set-up time setting means further includes gate means for supplying an output of a selected one of said plurality of second delay circuits on the basis of the multi-bit select signal inputted to said decoder circuit, said output corresponding to said write pulse signal when the device is in a write mode.

Claim 8

A semiconductor integrated circuit device according to claim 1, wherein said memory circuit is a multi-bit static random access memory which includes memory cells for storing data and writing circuits for writing predetermined data to selected memory cells, and wherein said write pulse generation circuit outputs said write pulse signal to said write circuits.

Claim 9

A semiconductor memory device comprising a write pulse generator and a memory circuit, wherein said semiconductor memory device comprises a first external terminal for receiving a first select signal and a second external terminal for receiving a second select signal, and wherein said write pulse generator comprises: first means, for receiving a clock signal and providing a first delay function, including a first delay circuit and a second delay circuit coupled to said first delay circuit, said first delay circuit receiving a signal based on said clock signal and outputting a first delay signal, and said second delay circuit receiving said first delay signal and outputting a second delay signal; first gate means, coupled to said first means, for receiving at least one of said clock signal, said first delay signal and said second delay signal and for outputting an internal pulse signal; a second means, for receiving said internal pulse signal and providing a second delay function, including a third delay circuit and a fourth delay circuit coupled to said third delay circuit, said third delay circuit receiving a signal based on said internal pulse signal and outputting a third delay signal, and said fourth delay circuit receiving said third delay signal and outputting a fourth delay signal; second gate means, coupled to said second means, for receiving at least one of said internal pulse signal, said third delay signal and said fourth delay signal and for outputting a write pulse signal; first decoding means, coupled to said first external terminal for receiving said first select signal, for effecting control of said first gate means which selects at least one of said clock signal, said first delay signal and said second delay signal as said internal pulse signal; and second decoding means, coupled to said second external terminal for receiving said second select signal, for effecting control of said second gate means which selects at least one of said internal pulse signal, said third delay signal and said fourth delay signal as said write pulse signal.

Claim 10

A semiconductor memory device comprising a write pulse generator and a memory circuit, wherein said semiconductor memory device comprises a first external terminal for receiving a first select signal and a second external terminal for receiving a second select signal, and wherein said write pulse generator comprises: first means, for receiving a clock signal and providing a first delay function, including a first delay circuit and a second delay circuit coupled to said first delay circuit, said first delay circuit receiving a signal based on said clock signal and outputting a first delay signal, and said second delay circuit receiving said first delay signal and outputting a second delay signal; first gate means, coupled to said first means, for receiving at least one of said clock signal, said first delay signal and said second delay signal and for outputting an internal pulse signal; a second means, for receiving said internal pulse signal and providing a second delay function, including a third delay circuit and a fourth delay circuit coupled to said third delay circuit, said third delay circuit receiving a signal based on said internal pulse signal and outputting a third delay signal, and said fourth delay circuit receiving said third delay signal and outputting a fourth delay signal; second gate means, coupled to said second means, for receiving at least one of said internal pulse signal, said third delay signal and said fourth delay signal and for outputting a write pulse signal; first decoding means, coupled to said first external terminal for receiving said first select signal, for effecting control of said first gate means which selects at least one of said clock signal, said first delay signal and said second delay signal as said internal pulse signal; and second decoding means, coupled to said second external terminal for receiving said second select signal, for effecting control of said second gate means which selects at least one of said internal pulse signal, said third delay signal and said fourth delay signal as said write pulse signal.

Claim 11

A semiconductor memory device according to claim 8, wherein said memory circuit is a static random access memory.

Claim 12

A semiconductor memory device according to claim 9, wherein said static random access memory includes a memory cell for storing data and a write circuit for writing predetermined data to said memory cell, and wherein said write pulse generator outputs said write pulse signal to said write circuit.

Claim 13

A semiconductor memory device according to claim 10, wherein said first delay function is a pulse width determining function and said second delay function is a set-up time determining function for said write pulse signal.

Claim 14

A semiconductor memory device according to claim 10, wherein said first and second select signals are multi-bit pulse width and multi-bit set-up time select control signals, respectively.

Claim 15

A semiconductor memory device according to claim 8, wherein said memory circuit is a multi-bit static random access memory which includes memory cells for storing data and writing circuits for writing predetermined data to selected memory cells, and wherein said write pulse generation circuit outputs said write pulse signal to said write circuits.

Claim 16

A semiconductor memory device according to claim 8, wherein said first delay function is a pulse width determining function and said second delay function is a set-up time determining function for said write pulse signal.

Claim 17

A semiconductor memory device according to claim 14, wherein said first and second select signals are multi-bit pulse width and multi-bit set-up time select control signals, respectively.

Claim 18

A semiconductor memory device according to claim 13, wherein said memory circuit is a multi-bit static random access memory which includes memory cells for storing data and writing circuits for writing predetermined data to selected memory cells, and wherein said write pulse generation circuit outputs said write pulse signal to said write circuits.