Write control circuit for a high-speed memory device

Claim 2

A write control circuit of a memory device comprising: a first receiving circuit for receiving a first write enable signal with a pulse duration equal to two write cycles; a second receiving circuit for receiving a second write enable signal with a pulse duration equal to two write cycles and having a phase difference equal to at least one write cycle relative to said first write enable signal; a converting circuit connected to said first and second receiving circuits for converting said first write enable signal into a first write signal with a pulse duration equal to one write cycle and said second write enable signal into a second write signal with a pulse duration equal to one write cycle and having a phase difference relative to said first write signal equal to the phase difference between said first and second write enable signals; and a generating circuit connected to said converting circuit and responsive to each of said first and second write signals for generating in each signal period of said first and second write signals a write execute signal for controlling execution of a write operation.

Claim 3

A write control circuit as claimed in claim 1, wherein said generating circuit comprises a third receiving circuit for receiving a first clock signal having a clock pulse interval equal to one write cycle, a pulse generating circuit responsive to said first clock signal for generating a train of pulses each having a duration equal to a pulse duration of said write execute signal and being synchronized with said first clock signal, and a first gate circuit connected to said converting circuit and said pulse generating circuit for transmitting one of said pulses generated by said pulse generating circuit in response to each of said first and second write signals.

Claim 4

A write control circuit as claimed in claim 1, wherein said generating circuit comprises a third receiving circuit for receiving a clock signal with a pulse duration and a pulse interval both equal to two write cycles, a delaying circuit for delaying said clock signal for a time equal to one write cycle, a logic circuit connected to said third receiving circuit and said delaying circuit for generating a gating signal having a gating signal pulse which lasts only when said clock signal and said delayed clock signal are in different logic states, and a gate circuit connected to said first and second receiving circuits and said logic circuit for transmitting part of said first write enable signal while an inverted gating signal pulse of said gating signal exists and for transmitting part of said second write enable signal while said gating signal pulse exists.

Claim 5

A write control circuit as claimed in claim 1, wherein said write cycle has the same length as a read cycle.

Claim 6

A write control circuit as claimed in claim 1, wherein the phase difference of said second write enable signal relative to said first write enable signal is equal to an odd number of write cycles.

Claim 7

An integrated circuit memory device which comprises a memory array, a read/write circuit connected to said memory array, and a write control circuit connected to said read/write circuit, said write control circuit comprising: a first receiving circuit for receiving a first write enable signal with a pulse duration equal to two write cycles; a second receiving circuit for receiving a second write enable signal with a pulse duration equal to two write cycles and having a phase difference equal to at least one write cycle relative to said first write enable signal; a third receiving circuit for receiving a clock signal having a clock pulse interval equal to one write cycle; a converting circuit connected to said first and second receiving circuits for converting said first write enable signal into a first write signal with a pulse duration equal to one write cycle and said second write enable signal into a second write signal with a pulse duration equal to one write cycle and having a phase difference relative to said first write signal equal to the phase difference between said first and second write enable signals; a pulse generating circuit connected to said third receiving circuit for generating a train of write control pulses in synchronism with said clock signal; and a gate circuit connected to said converting circuit, said pulse generating circuit and said read/write circuit for transmitting, in response to each of said first and second write signals, one of said write control pulses to said read/write circuit.

Claim 8

An integrated circuit memory device which comprises a memory array, a read/write circuit connected to said memory array, and a write control circuit connected to said read/write circuit, said write control circuit comprising: a first receiving circuit for receiving a first write enable signal with a pulse duration equal to two write cycles; a second receiving circuit for receiving a second write enable signal with a pulse duration equal to two write cycles and having a phase difference equal to at least one write cycle relative to said first write enable signal; a third receiving circuit for receiving a clock signal having a clock pulse interval equal to one write cycle; a converting circuit connected to said first and second receiving circuits for converting said first write enable signal into a first write signal with a pulse duration equal to one write cycle and said second write enable signal into a second write signal with a pulse duration equal to one write cycle and having a phase difference relative to said first write signal equal to the phase difference between said first and second write enable signals; a pulse generating circuit connected to said third receiving circuit for generating a train of write control pulses in synchronism with said clock signal; and a gate circuit connected to said converting circuit, said pulse generating circuit and said read/write circuit for transmitting, in response to each of said first and second write signals, one of said write control pulses to said read/write circuit.

Claim 9

A memory device as claimed in claim 6, wherein the phase difference of said second write enable signal relative to said first write enable signal is equal to an odd number of write cycles.